Adds BasisTanslator, UnrollCustomDefinitions to default levels.

[kdk]

Resolves #3146
Resolves #3086

Summary

• Fix free param calculation in standard gates to_matrix test.

Previous code mis-calculated the number of available free parameters
from the gate signature, resulting in creation of gates like
XGate(label=0.1). These would cause errors if the circuits containing
these gates were drawn.

• Remove definition for C3XGate, C4XGate due to name conflict with MCXGate.

• Add Rz->RX,RY, U3->RX,RY, CX->RXX to StandardEquivalenceLibrary.

Updates BasisTranslator-Unroller compatability test
test_basis_translator.TestUnrollerCompatibility.test_unroll_all_instructions
to verify the generated circuit is equivalent (with snapshot,
measure instructions removed) as the circuit transpiled by the
BasisTranslator is no longer gate-for-gate equal with that of the
Unroller.

• Add SynthesizeUnitaries and BasisTranslator into default levels.

on-hold for #4442 .

Details and comments

[ajavadia]

Does this resolve #3146 and #3086? I think if we add a CX -> CZ and CX -> iSWAP then we have enabled some basic common basis for now.

[kdk]

Does this resolve #3146 and #3086? I think if we add a CX -> CZ and CX -> iSWAP then we have enabled some basic common basis for now.

This resolves #3146, and most of #3086 (except for generalizing commutative cancellation).

[ajavadia]

Ok I marked it as resolving those two issues (generalizing commutative cancellation seems like a separate issue)

Can you add tests for rewriting some general circuits in terms of CZ and iSWAP?

[ajavadia]

I made 2 comments otherwise I'm good with this.

[ajavadia]

Since alternate basis are now supported by preset passmanagers, I think they should be supported by individual passes inside those passmanagers too - not just the two newly added passes. For example level 3 is supposed to do block collection and resynthesis to avoid redundant applications of 2-qubit gates. At the moment, however, I think this really just works for CNOTs.

Running this code:

from qiskit.circuit.library import QuantumVolume
from qiskit import transpile
qv_model = QuantumVolume(3, seed=3)
qv_iswap = transpile(qv_model, basis_gates=['iswap', 'u3'], optimization_level=3)
qv_iswap.draw('mpl', fold=100)

I get the circuit below, but all those iswap chains of 6 should be reduced to at most 3 using the block collection/resynthesis passes.

[ajavadia]

This looks good. For 2-qubit gates I think this is doing a reasonable job, but for 1-qubit gates there are still inefficiencies. I fix this as part of #3658

from qiskit import *
qc = QuantumCircuit(2)
qc.cx(0, 1)
qc.cx(1, 0)

out = transpile(qc, basis_gates=['iswap', 'rx', 'rz'], optimization_level=3)