NAvi349

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Navinkumar K NAvi349

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Final Year B. Tech ECE student at Puducherry Technological University.

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Puducherry, India
https://www.linkedin.com/in/navinkumar-k-208721199/

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NAvi349/README.md

Hi 👋, I'm Navinkumar

VLSI Enthusiast

🌱 List of Projects:
- RISC - V Core on Open FPGA Architecture
- RISC-V_27 - System Verilog based RISC-V Single Core processor with 5 stage pipeline and hazard handling
- MYTH - TL - Verilog based RISC-V 5 stage Pipelined Single Core Processor with hazard handling
- 16-bit Reversible logic Carry Look Ahead Adder
- Transmission Gate based 1 - bit Full adder
🔭 I’m currently learning FPGA Based Design Implementation Techniques

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riscv-proc riscv-proc Public

32-bit 5-Stage Pipelined RISC V RV32I Core

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rtl-sky130-ws rtl-sky130-ws Public

This is a documentation of the work done as part of the 5 - day RTL Design Workshop using Verilog with SKY130 Technology

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mixed-riscv-soc mixed-riscv-soc Public

This repository contains the work as part of the 1 day workshop on Mixed-Signal RISC-V based SoC on FPGA sponsored by the OSFPGA Foundation

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osfpga-fda osfpga-fda Public

This repository contains the work done as part of the 5 Workshop on FPGA - Fabric, Design and Architecture sponsored by the OSFPGA Foundation

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trans-full-adder trans-full-adder Public

1 - bit Full Adder implementation using Transmission Gate Logic and Conventional Inverter.

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