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Add GPU project chipyard changes #2190
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Original file line number | Diff line number | Diff line change |
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|
@@ -48,7 +48,7 @@ | |
url = https://github.com/ucb-bar/rocc-acc-utils.git | ||
[submodule "generators/rocket-chip"] | ||
path = generators/rocket-chip | ||
url = https://github.com/chipsalliance/rocket-chip.git | ||
url = https://github.com/richardyrh/rocket-chip.git | ||
[submodule "generators/rocket-chip-blocks"] | ||
path = generators/rocket-chip-blocks | ||
url = https://github.com/chipsalliance/rocket-chip-blocks.git | ||
|
@@ -157,3 +157,6 @@ | |
[submodule "generators/tacit"] | ||
path = generators/tacit | ||
url = https://github.com/ucb-bar/tacit.git | ||
[submodule "generators/radiance"] | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. You should add radiance to the .github/scripts/check-commit.sh script |
||
path = generators/radiance | ||
url = https://github.com/ucb-bar/radiance.git |
Original file line number | Diff line number | Diff line change |
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|
@@ -16,6 +16,8 @@ HELP_COMPILATION_VARIABLES += \ | |
" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ | ||
" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ | ||
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ | ||
" EXTRA_SIM_OUT_NAME = additional suffix appended to the simulation .out log filename" \ | ||
" EXTRA_SIM_PREPROC_DEFINES = additional defines passed to the simulator" \ | ||
" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \ | ||
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ | ||
" MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \ | ||
|
@@ -26,6 +28,7 @@ EXTRA_SIM_CXXFLAGS ?= | |
EXTRA_SIM_LDFLAGS ?= | ||
EXTRA_SIM_SOURCES ?= | ||
EXTRA_SIM_REQS ?= | ||
EXTRA_SIM_OUT_NAME ?= | ||
|
||
ifneq ($(ASPECTS), ) | ||
comma = , | ||
|
@@ -67,6 +70,7 @@ include $(base_dir)/generators/ibex/ibex.mk | |
include $(base_dir)/generators/ara/ara.mk | ||
include $(base_dir)/generators/tracegen/tracegen.mk | ||
include $(base_dir)/generators/nvdla/nvdla.mk | ||
include $(base_dir)/generators/radiance/radiance.mk | ||
include $(base_dir)/tools/torture.mk | ||
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||
######################################################################################### | ||
|
@@ -233,6 +237,8 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS | |
--model-module-name $(MODEL) \ | ||
--out-dut-smems-conf $(TOP_SMEMS_CONF) \ | ||
--out-model-smems-conf $(MODEL_SMEMS_CONF) | ||
# for blackboxed SRAMs: define mem here and use generated module name in blackbox source | ||
-[ -f $(base_dir)/vlsi/add.mem.conf ] && cat $(base_dir)/vlsi/add.mems.conf >> $(TOP_SMEMS_CONF) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I think there's a cleaner way to do this. What if you have the generator emit a supplementary file I don't like having this magic file in the vlsi/ directory. |
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# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs | ||
TOP_MACROCOMPILER_MODE ?= --mode synflops | ||
|
@@ -305,15 +311,15 @@ get_loadarch_flag = +loadarch=$(subst mem.elf,loadarch,$(1)) | |
endif | ||
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# get the output path base name for simulation outputs, First arg is the binary | ||
get_sim_out_name = $(output_dir)/$(call get_out_name,$(1)) | ||
get_sim_out_name = $(output_dir)/$(call get_out_name,$(1))$(if $(EXTRA_SIM_OUT_NAME),.$(EXTRA_SIM_OUT_NAME),) | ||
# sim flags that are common to run-binary/run-binary-fast/run-binary-debug | ||
get_common_sim_flags = $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(call get_loadmem_flag,$(1)) $(call get_loadarch_flag,$(1)) | ||
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.PHONY: %.run %.run.debug %.run.fast | ||
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# run normal binary with hardware-logged insn dissassembly | ||
run-binary: check-binary $(BINARY).run | ||
run-binaries: check-binaries $(addsuffix .run,$(BINARIES)) | ||
run-binaries: check-binaries $(addsuffix .run,$(wildcard $(BINARIES))) | ||
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%.run: %.check-exists $(SIM_PREREQ) | $(output_dir) | ||
(set -o pipefail && $(NUMA_PREFIX) $(sim) \ | ||
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@@ -327,7 +333,7 @@ run-binaries: check-binaries $(addsuffix .run,$(BINARIES)) | |
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# run simulator as fast as possible (no insn disassembly) | ||
run-binary-fast: check-binary $(BINARY).run.fast | ||
run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES)) | ||
run-binaries-fast: check-binaries $(addsuffix .run.fast,$(wildcard $(BINARIES))) | ||
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%.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir) | ||
(set -o pipefail && $(NUMA_PREFIX) $(sim) \ | ||
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@@ -340,7 +346,9 @@ run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES)) | |
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# run simulator with as much debug info as possible | ||
run-binary-debug: check-binary $(BINARY).run.debug | ||
run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES)) | ||
run-binary-debug-bg: check-binary $(BINARY).run.debug.bg | ||
run-binaries-debug: check-binaries $(addsuffix .run.debug,$(wildcard $(BINARIES))) | ||
run-binaries-debug-bg: check-binaries $(addsuffix .run.debug.bg,$(wildcard $(BINARIES))) | ||
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%.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir) | ||
ifeq (1,$(DUMP_BINARY)) | ||
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@@ -356,6 +364,19 @@ endif | |
$(BINARY_ARGS) \ | ||
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) | ||
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%.run.debug.bg: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir) | ||
if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi | ||
(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \ | ||
$(PERMISSIVE_ON) \ | ||
$(call get_common_sim_flags,$*) \ | ||
$(VERBOSE_FLAGS) \ | ||
$(call get_waveform_flag,$(call get_sim_out_name,$*)) \ | ||
$(PERMISSIVE_OFF) \ | ||
$* \ | ||
$(BINARY_ARGS) \ | ||
</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) >$(call get_sim_out_name,$*).log \ | ||
& echo "PID=$$!") | ||
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run-fast: run-asm-tests-fast run-bmark-tests-fast | ||
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######################################################################################### | ||
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,20 @@ | ||
package chipyard | ||
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import org.chipsalliance.cde.config.{Config} | ||
import freechips.rocketchip.prci.AsynchronousCrossing | ||
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class MemtraceCoreConfig extends Config( | ||
// Memtrace | ||
new radiance.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", | ||
traceHasSource = false) ++ | ||
// new radiance.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.lane32.trace", | ||
// traceHasSource = false) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ | ||
new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 8) ++ | ||
// L2 | ||
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ | ||
new freechips.rocketchip.subsystem.WithNBanks(4) ++ | ||
new chipyard.config.WithSystemBusWidth(16 * 8) ++ | ||
new chipyard.NoCoresConfig | ||
) | ||
|
Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,157 @@ | ||
package chipyard | ||
|
||
import chipyard.config.AbstractConfig | ||
import chipyard.stage.phases.TargetDirKey | ||
import freechips.rocketchip.devices.tilelink.BootROMLocated | ||
import freechips.rocketchip.resources.BigIntHexContext | ||
import freechips.rocketchip.subsystem._ | ||
import org.chipsalliance.cde.config.Config | ||
import radiance.subsystem.RadianceGemminiDataType | ||
|
||
// ---------------- | ||
// Radiance Configs | ||
// ---------------- | ||
|
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// aliases for virgo | ||
class VirgoConfig extends RadianceClusterConfig | ||
class VirgoFP16Config extends RadianceFP16ClusterConfig | ||
class VirgoHopperConfig extends Radiance4CFP16ClusterConfig | ||
class VirgoFlashConfig extends RadianceClusterConfig | ||
class VirgoSynConfig extends RadianceClusterSynConfig | ||
class VirgoFP16SynConfig extends RadianceFP16ClusterSynConfig | ||
class VirgoHopperSynConfig extends Radiance4CFP16ClusterSynConfig | ||
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class RadianceBaseConfig extends Config( | ||
// NOTE: when changing these, remember to change NUM_CORES/THREADS/WARPS in | ||
// the verilog source as well! | ||
new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++ | ||
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ | ||
new WithExtMemSize(BigInt("80000000", 16)) ++ | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Nit: leaving the full package paths here is cleaner I think (including chipyard.AbstractConfig) |
||
new WithRadBootROM() ++ | ||
new radiance.subsystem.WithRadianceSimParams(true) ++ | ||
new WithCacheBlockBytes(64) ++ | ||
new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ | ||
new freechips.rocketchip.subsystem.WithEdgeDataBits(256) ++ | ||
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new chipyard.config.WithPeripheryBusFrequency(400.0) ++ | ||
new chipyard.config.WithMemoryBusFrequency(400.0) ++ | ||
new chipyard.config.WithControlBusFrequency(400.0) ++ | ||
new chipyard.config.WithSystemBusFrequency(400.0) ++ | ||
new chipyard.config.WithFrontBusFrequency(400.0) ++ | ||
new chipyard.config.WithOffchipBusFrequency(400.0) ++ | ||
new chipyard.harness.WithHarnessBinderClockFreqMHz(400.0) ++ | ||
new AbstractConfig) | ||
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||
class RadianceFP16ClusterConfig extends Config( | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++ | ||
new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++ | ||
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ | ||
new radiance.subsystem.WithRadianceCluster(0) ++ | ||
new RadianceBaseConfig) | ||
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class Radiance8B8WFP16ClusterConfig extends Config( | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++ | ||
new radiance.subsystem.WithRadianceCores(8, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, useVxCache = false) ++ | ||
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 8, numWords = 8) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ | ||
new radiance.subsystem.WithRadianceCluster(0) ++ | ||
new RadianceBaseConfig) | ||
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||
class Radiance4CFP16ClusterConfig extends Config( | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++ | ||
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = true, useVxCache = false) ++ | ||
// new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 16, | ||
// memType = radiance.subsystem.TwoReadOneWrite, | ||
// serializeUnaligned = radiance.subsystem.CoreSerialized) ++ | ||
// NOTE: Hopper Tensor Core does not work with 16-word config due to the | ||
// address alignment requirement | ||
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 8) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ | ||
new radiance.subsystem.WithRadianceCluster(0) ++ | ||
new RadianceBaseConfig) | ||
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||
class RadianceClusterConfig extends Config( | ||
// important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ | ||
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = false, tensorCoreDecoupled = false, useVxCache = false) ++ | ||
// new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++ | ||
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 256 << 10/*KBytes*/, numBanks = 8, numWords = 8, | ||
// memType = radiance.subsystem.TwoReadOneWrite, | ||
serializeUnaligned = radiance.subsystem.CoreSerialized) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++ | ||
new radiance.subsystem.WithRadianceCluster(0) ++ | ||
new RadianceBaseConfig) | ||
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class RadianceClusterSmem16KConfig extends Config( | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++ | ||
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++ | ||
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10/*KBytes*/, numBanks = 4, numWords = 8) ++ // serializeUnaligned: false | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ | ||
new radiance.subsystem.WithRadianceCluster(0) ++ | ||
new RadianceBaseConfig) | ||
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class RadianceTwoClustersSmem16KConfig extends Config( | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++ | ||
new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++ | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(1), dim = 8, accSizeInKB = 4, tileSize = 4) ++ | ||
new radiance.subsystem.WithRadianceCores(2, location = InCluster(1), useVxCache = false) ++ | ||
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10, numBanks = 4, numWords = 8) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ | ||
new radiance.subsystem.WithRadianceCluster(0) ++ | ||
new radiance.subsystem.WithRadianceCluster(1) ++ | ||
new RadianceBaseConfig) | ||
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class RadianceBigLittleClusterConfig extends Config( | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 4, accSizeInKB = 16, tileSize = 16) ++ | ||
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ | ||
new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++ | ||
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ | ||
new radiance.subsystem.WithRadianceCluster(0) ++ | ||
new RadianceBaseConfig) | ||
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class RadianceClusterSynConfig extends Config( | ||
new radiance.subsystem.WithRadianceSimParams(false) ++ | ||
new RadianceClusterConfig) | ||
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class RadianceFP16ClusterSynConfig extends Config( | ||
new radiance.subsystem.WithRadianceSimParams(false) ++ | ||
new RadianceFP16ClusterConfig) | ||
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class Radiance4CFP16ClusterSynConfig extends Config( | ||
new radiance.subsystem.WithRadianceSimParams(false) ++ | ||
new Radiance4CFP16ClusterConfig) | ||
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class RadianceBigLittleClusterSynConfig extends Config( | ||
new radiance.subsystem.WithRadianceSimParams(false) ++ | ||
new RadianceBigLittleClusterConfig) | ||
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class RadianceNoCacheConfig extends Config( | ||
new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 8) ++ | ||
new RadianceBaseConfig) | ||
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class RadianceNoCoalConfig extends Config( | ||
new radiance.subsystem.WithRadianceCores(1, useVxCache = false) ++ | ||
new radiance.subsystem.WithVortexL1Banks(nBanks = 1)++ | ||
new RadianceBaseConfig) | ||
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class RadianceEmulatorConfig extends Config( | ||
new radiance.subsystem.WithEmulatorCores(1, useVxCache = false) ++ | ||
new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 4) ++ | ||
new AbstractConfig) | ||
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class RadianceFuzzerConfig extends Config( | ||
new radiance.subsystem.WithFuzzerCores(1, useVxCache = false) ++ | ||
new radiance.subsystem.WithCoalescer(nNewSrcIds = 2) ++ | ||
new radiance.subsystem.WithSimtConfig(nMemLanes = 4, nSrcIds = 2) ++ | ||
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ | ||
new AbstractConfig) |
Original file line number | Diff line number | Diff line change |
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|
@@ -38,4 +38,5 @@ SIM_PREPROC_DEFINES = \ | |
+define+RANDOMIZE_MEM_INIT \ | ||
+define+RANDOMIZE_REG_INIT \ | ||
+define+RANDOMIZE_GARBAGE_ASSIGN \ | ||
+define+RANDOMIZE_INVALID_ASSIGN | ||
+define+RANDOMIZE_INVALID_ASSIGN \ | ||
$(EXTRA_SIM_PREPROC_DEFINES) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Add this to HELP_COMPILATION_VARIABLES in common.mk |
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Revert this.