ADD: update to match new submodule tacit

.gitmodules

@@ -157,3 +157,6 @@
 [submodule "software/tacit_decoder"]
 	path = software/tacit_decoder
 	url = [email protected]:ucb-bar/tacit_decoder.git
+[submodule "generators/tacit"]
+	path = generators/tacit
+	url = [email protected]:ucb-bar/tacit.git

build.sbt

@@ -158,7 +158,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
-    compressacc, saturn, ara, firrtl2_bridge, vexiiriscv)
+    compressacc, saturn, ara, firrtl2_bridge, vexiiriscv, tacit)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(
     libraryDependencies ++= Seq(
@@ -253,6 +253,11 @@ lazy val nvdla = (project in file("generators/nvdla"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+lazy val tacit = (project in file("generators/tacit"))
+  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)
+
 lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
   .dependsOn(rocketchip, rocc_acc_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink._
 
 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
-  with freechips.rocketchip.trace.CanHaveTraceSinkDMA
+  with tacit.CanHaveTraceSinkDMA
   with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
   with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
   with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -117,8 +117,8 @@ class SV48RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class LTraceEncoderRocketConfig extends Config(
-  new freechips.rocketchip.trace.WithTraceSinkDMA(1) ++
-  new freechips.rocketchip.trace.WithTraceSinkAlways(0) ++
+  new tacit.WithTraceSinkDMA(1) ++
+  new tacit.WithTraceSinkAlways(0) ++
   new chipyard.config.WithArbiterMonitor ++
   new chipyard.config.WithLTraceEncoder ++
   new chipyard.config.WithNPerfCounters(29) ++

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -14,7 +14,8 @@ import ibex.{IbexTileAttachParams}
 import vexiiriscv.{VexiiRiscvTileAttachParams}
 import testchipip.cosim.{TracePortKey, TracePortParams}
 import barf.{TilePrefetchingMasterPortParams}
-import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams, TacitEncoder}
+import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams}
+import tacit.{TacitEncoder}
 
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {