ADD: configuration to match updated rocketchip API

ucb-bar · Jan 24, 2025 · 29800e2 · 29800e2
1 parent 349885a
commit 29800e2
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Showing 2 changed files with 16 additions and 8 deletions.
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -119,6 +119,7 @@ class SV48RocketConfig extends Config(
 class LTraceEncoderRocketConfig extends Config(
   new freechips.rocketchip.trace.WithTraceSinkDMA(1) ++
   new freechips.rocketchip.trace.WithTraceSinkAlways(0) ++
+  new chipyard.config.WithArbiterMonitor ++
   new chipyard.config.WithLTraceEncoder ++
   new chipyard.config.WithNPerfCounters(29) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++

diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -6,14 +6,15 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
+import freechips.rocketchip.diplomacy._
 
 import cva6.{CVA6TileAttachParams}
 import sodor.common.{SodorTileAttachParams}
 import ibex.{IbexTileAttachParams}
 import vexiiriscv.{VexiiRiscvTileAttachParams}
 import testchipip.cosim.{TracePortKey, TracePortParams}
 import barf.{TilePrefetchingMasterPortParams}
-import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams}
+import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams, TacitEncoder}
 
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -68,21 +69,27 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
 class WithLTraceEncoder extends Config((site, here, up) => {
    case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
      case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      ltrace = Some(TraceEncoderParams(
-        coreParams = TraceCoreParams(
+      traceParams = Some(TraceEncoderParams(
+        encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
+        buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams(
           nGroups = 1,
           iretireWidth = 1,
           xlen = tp.tileParams.core.xLen,
           iaddrWidth = tp.tileParams.core.xLen
-         ),
-         bufferDepth = 16,
-         encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
-         useArbiterMonitor = true
-       )),
+        ), 16)(p)),
+        useArbiterMonitor = false
+      )),
       core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
    }
  })
 
+class WithArbiterMonitor extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      traceParams = Some(tp.tileParams.traceParams.get.copy(useArbiterMonitor = true))))
+  }
+})
+
 class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(