Minor rtl optimizations and cleanups (#1174)

stnolting · Feb 1, 2025 · 2be7f00 · 2be7f00
2 parents fe0eade + 5aea292
commit 2be7f00
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 01.02.2025 | 1.11.0.5 | minor rtl optimizations and cleanups; :warning: remove DMA "fence" feature | [#1174](https://github.com/stnolting/neorv32/pull/1174) |
 | 28.01.2025 | 1.11.0.4 | :bug: fix crt0's entry address being overridden by core0's constructors (that do not backup any registers) | [#1172](https://github.com/stnolting/neorv32/pull/1172) |
 | 28.01.2025 | 1.11.0.3 | :bug: fix BOOTROM addressing (index was out-of-range) | [#1171](https://github.com/stnolting/neorv32/pull/1171) |
 | 24.01.2025 | 1.11.0.2 | :warning: rename JEDEC ID generic; minor rtl edits and optimizations | [#1168](https://github.com/stnolting/neorv32/pull/1168) |

diff --git a/docs/datasheet/soc_dma.adoc b/docs/datasheet/soc_dma.adoc
@@ -119,13 +119,6 @@ The DMA transfer will start if a **rising edge** is detected on the configured F
 once even if the selected FIRQ channel keeps pending.
 
 
-**Memory Barrier / Fence Operation**
-
-Optionally, the DMA can issue a FENCE request to the downstream memory system when a transfer has been completed
-without errors. This can be used to re-sync caches (flush and reload) and buffers to maintain data coherency.
-This automatic fencing is enabled by the setting the control register's `DMA_CTRL_FENCE` bit.
-
-
 **DMA Interrupt**
 
 The DMA features a single CPU interrupt that is triggered when the programmed transfer has completed. This
@@ -141,10 +134,9 @@ register).
 [options="header",grid="all"]
 |=======================
 | Address | Name [C] | Bit(s), Name [C] | R/W | Function
-.12+<| `0xffed0000` .12+<| `CTRL` <|`0`     `DMA_CTRL_EN`                                   ^| r/w <| DMA module enable
+.11+<| `0xffed0000` .11+<| `CTRL` <|`0`     `DMA_CTRL_EN`                                   ^| r/w <| DMA module enable
                                   <|`1`     `DMA_CTRL_AUTO`                                 ^| r/w <| Enable automatic mode (FIRQ-triggered)
-                                  <|`2`     `DMA_CTRL_FENCE`                                ^| r/w <| Issue a downstream FENCE operation when DMA transfer completes (without errors)
-                                  <|`7:3`   _reserved_                                      ^| r/- <| reserved, read as zero
+                                  <|`7:2`   _reserved_                                      ^| r/- <| reserved, read as zero
                                   <|`8`     `DMA_CTRL_ERROR_RD`                             ^| r/- <| Error during read access, clears when starting a new transfer
                                   <|`9`     `DMA_CTRL_ERROR_WR`                             ^| r/- <| Error during write access, clears when starting a new transfer
                                   <|`10`    `DMA_CTRL_BUSY`                                 ^| r/- <| DMA transfer in progress

diff --git a/rtl/core/neorv32_application_image.vhd b/rtl/core/neorv32_application_image.vhd
@@ -1,7 +1,7 @@
 -- The NEORV32 RISC-V Processor - github.com/stnolting/neorv32
 -- Auto-generated memory initialization image (for internal IMEM)
 -- Source: demo_blink_led/build/main.bin
--- Built: 15.01.2025 21:11:45
+-- Built: 01.02.2025 15:17:07
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -11,7 +11,7 @@ use neorv32.neorv32_package.all;
 
 package neorv32_application_image is
 
-constant application_init_size_c  : natural := 1204; -- bytes
+constant application_init_size_c  : natural := 1208; -- bytes
 constant application_init_image_c : mem32_t := (
 x"f14020f3",
 x"80002217",
@@ -23,11 +23,11 @@ x"000022b7",
 x"80028293",
 x"30029073",
 x"00000317",
-x"18830313",
+x"18c30313",
 x"30531073",
 x"30401073",
 x"00000397",
-x"48038393",
+x"48438393",
 x"80000417",
 x"fc440413",
 x"80000497",
@@ -36,8 +36,7 @@ x"80000517",
 x"fb450513",
 x"80000597",
 x"fac58593",
-x"00000617",
-x"19060613",
+x"00000613",
 x"00000693",
 x"00000713",
 x"00000793",
@@ -63,7 +62,7 @@ x"01878793",
 x"30579073",
 x"30446073",
 x"30046073",
-x"0dc0006f",
+x"0e40006f",
 x"fff40737",
 x"00072223",
 x"bc1026f3",
@@ -74,7 +73,7 @@ x"30200073",
 x"bc102173",
 x"bc102673",
 x"bc171073",
-x"0540006f",
+x"05c0006f",
 x"00838e63",
 x"00945c63",
 x"0003a783",
@@ -87,14 +86,16 @@ x"00052023",
 x"00450513",
 x"ff5ff06f",
 x"00000417",
-x"39040413",
+x"39840413",
 x"00000497",
-x"38848493",
+x"39048493",
 x"00945a63",
 x"00042083",
 x"000080e7",
 x"00440413",
 x"ff1ff06f",
+x"00000617",
+x"0ac60613",
 x"0ff0000f",
 x"0000100f",
 x"30029073",