⚠️ [dma] remove "fence" feature

stnolting · Feb 1, 2025 · 5aea292 · 5aea292
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Showing 8 changed files with 9 additions and 62 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,7 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
-| 01.02.2025 | 1.11.0.5 | minor rtl optimizations and cleanups | [#1174](https://github.com/stnolting/neorv32/pull/1174) |
+| 01.02.2025 | 1.11.0.5 | minor rtl optimizations and cleanups; :warning: remove DMA "fence" feature | [#1174](https://github.com/stnolting/neorv32/pull/1174) |
 | 28.01.2025 | 1.11.0.4 | :bug: fix crt0's entry address being overridden by core0's constructors (that do not backup any registers) | [#1172](https://github.com/stnolting/neorv32/pull/1172) |
 | 28.01.2025 | 1.11.0.3 | :bug: fix BOOTROM addressing (index was out-of-range) | [#1171](https://github.com/stnolting/neorv32/pull/1171) |
 | 24.01.2025 | 1.11.0.2 | :warning: rename JEDEC ID generic; minor rtl edits and optimizations | [#1168](https://github.com/stnolting/neorv32/pull/1168) |

diff --git a/docs/datasheet/soc_dma.adoc b/docs/datasheet/soc_dma.adoc
@@ -119,13 +119,6 @@ The DMA transfer will start if a **rising edge** is detected on the configured F
 once even if the selected FIRQ channel keeps pending.
 
 
-**Memory Barrier / Fence Operation**
-
-Optionally, the DMA can issue a FENCE request to the downstream memory system when a transfer has been completed
-without errors. This can be used to re-sync caches (flush and reload) and buffers to maintain data coherency.
-This automatic fencing is enabled by the setting the control register's `DMA_CTRL_FENCE` bit.
-
-
 **DMA Interrupt**
 
 The DMA features a single CPU interrupt that is triggered when the programmed transfer has completed. This
@@ -141,10 +134,9 @@ register).
 [options="header",grid="all"]
 |=======================
 | Address | Name [C] | Bit(s), Name [C] | R/W | Function
-.12+<| `0xffed0000` .12+<| `CTRL` <|`0`     `DMA_CTRL_EN`                                   ^| r/w <| DMA module enable
+.11+<| `0xffed0000` .11+<| `CTRL` <|`0`     `DMA_CTRL_EN`                                   ^| r/w <| DMA module enable
                                   <|`1`     `DMA_CTRL_AUTO`                                 ^| r/w <| Enable automatic mode (FIRQ-triggered)
-                                  <|`2`     `DMA_CTRL_FENCE`                                ^| r/w <| Issue a downstream FENCE operation when DMA transfer completes (without errors)
-                                  <|`7:3`   _reserved_                                      ^| r/- <| reserved, read as zero
+                                  <|`7:2`   _reserved_                                      ^| r/- <| reserved, read as zero
                                   <|`8`     `DMA_CTRL_ERROR_RD`                             ^| r/- <| Error during read access, clears when starting a new transfer
                                   <|`9`     `DMA_CTRL_ERROR_WR`                             ^| r/- <| Error during write access, clears when starting a new transfer
                                   <|`10`    `DMA_CTRL_BUSY`                                 ^| r/- <| DMA transfer in progress

diff --git a/rtl/core/neorv32_dma.vhd b/rtl/core/neorv32_dma.vhd
@@ -43,7 +43,6 @@ architecture neorv32_dma_rtl of neorv32_dma is
   -- control and status register bits --
   constant ctrl_en_c           : natural :=  0; -- r/w: DMA enable
   constant ctrl_auto_c         : natural :=  1; -- r/w: enable FIRQ-triggered transfer
-  constant ctrl_fence_c        : natural :=  2; -- r/w: issue FENCE operation when DMA is done
   --
   constant ctrl_error_rd_c     : natural :=  8; -- r/-: error during read transfer
   constant ctrl_error_wr_c     : natural :=  9; -- r/-: error during write transfer
@@ -64,7 +63,6 @@ architecture neorv32_dma_rtl of neorv32_dma is
   type cfg_t is record
     enable    : std_ulogic; -- DMA enabled when set
     auto      : std_ulogic; -- FIRQ-driven auto transfer
-    fence     : std_ulogic; -- issue FENCE operation when DMA is done
     firq_sel  : std_ulogic_vector(3 downto 0);  -- FIRQ trigger select
     firq_type : std_ulogic; -- trigger on FIRQ rising-edge (0) or high-level (1)
     src_base  : std_ulogic_vector(31 downto 0); -- source base address
@@ -115,7 +113,6 @@ begin
       bus_rsp_o     <= rsp_terminate_c;
       cfg.enable    <= '0';
       cfg.auto      <= '0';
-      cfg.fence     <= '0';
       cfg.firq_sel  <= (others => '0');
       cfg.firq_type <= '0';
       cfg.src_base  <= (others => '0');
@@ -142,7 +139,6 @@ begin
           if (bus_req_i.addr(3 downto 2) = "00") then -- control and status register
             cfg.enable    <= bus_req_i.data(ctrl_en_c);
             cfg.auto      <= bus_req_i.data(ctrl_auto_c);
-            cfg.fence     <= bus_req_i.data(ctrl_fence_c);
             cfg.done      <= '0'; -- clear on write access
             cfg.firq_type <= bus_req_i.data(ctrl_firq_type_c);
             cfg.firq_sel  <= bus_req_i.data(ctrl_firq_sel_msb_c downto ctrl_firq_sel_lsb_c);
@@ -166,7 +162,6 @@ begin
             when "00" => -- control and status register
               bus_rsp_o.data(ctrl_en_c)        <= cfg.enable;
               bus_rsp_o.data(ctrl_auto_c)      <= cfg.auto;
-              bus_rsp_o.data(ctrl_fence_c)     <= cfg.fence;
               bus_rsp_o.data(ctrl_error_rd_c)  <= engine.err_rd;
               bus_rsp_o.data(ctrl_error_wr_c)  <= engine.err_wr;
               bus_rsp_o.data(ctrl_busy_c)      <= engine.busy;
@@ -305,12 +300,12 @@ begin
   engine.busy <= '0' when (engine.state = S_IDLE) else '1';
 
   -- bus output --
-  dma_req_o.priv  <= priv_mode_m_c; -- DMA accesses are always privileged
-  dma_req_o.src   <= '0'; -- source = data access
   dma_req_o.addr  <= engine.src_addr when (engine.state = S_READ) else engine.dst_addr;
+  dma_req_o.src   <= '0'; -- source = data access
+  dma_req_o.priv  <= priv_mode_m_c; -- DMA accesses are always privileged
   dma_req_o.amo   <= '0'; -- no atomic memory operation possible
   dma_req_o.amoop <= (others => '0'); -- no atomic memory operation possible
-  dma_req_o.fence <= cfg.enable and cfg.fence and engine.done; -- issue FENCE operation when transfer is done
+  dma_req_o.fence <= '0'; -- no fences
   dma_req_o.sleep <= '1' when (engine.state = S_IDLE) else '0'; -- idle = sleep mode
   dma_req_o.debug <= '0'; -- can never ever be in debug mode
 

diff --git a/sw/example/demo_dma/main.c b/sw/example/demo_dma/main.c
@@ -1,7 +1,7 @@
 // ================================================================================ //
 // The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
 // Copyright (c) NEORV32 contributors.                                              //
-// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  //
+// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  //
 // Licensed under the BSD-3-Clause license, see LICENSE for details.                //
 // SPDX-License-Identifier: BSD-3-Clause                                            //
 // ================================================================================ //
@@ -71,10 +71,6 @@ int main() {
   // enable DMA
   neorv32_dma_enable();
 
-  // issue a FENCE operation when the DMA transfer completes (without errors); this
-  // will re-sync / flush and reload) all **DOWNSTREAM** caches
-  neorv32_dma_fence_enable();
-
   // initialize and data arrays
   dma_src[0] = 0x66778899UL;
   dma_src[1] = 0x22334455UL;

diff --git a/sw/example/processor_check/main.c b/sw/example/processor_check/main.c
@@ -1448,7 +1448,6 @@ int main() {
 
     // enable DMA, auto-fencing and according FIRQ channel
     neorv32_dma_enable();
-    neorv32_dma_fence_enable();
     neorv32_cpu_csr_write(CSR_MIE, 1 << DMA_FIRQ_ENABLE);
 
     // setup source data

diff --git a/sw/lib/include/neorv32_dma.h b/sw/lib/include/neorv32_dma.h
@@ -1,18 +1,14 @@
 // ================================================================================ //
 // The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
 // Copyright (c) NEORV32 contributors.                                              //
-// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  //
+// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  //
 // Licensed under the BSD-3-Clause license, see LICENSE for details.                //
 // SPDX-License-Identifier: BSD-3-Clause                                            //
 // ================================================================================ //
 
 /**
  * @file neorv32_dma.h
  * @brief Direct Memory Access Controller (DMA) HW driver header file.
- *
- * @note These functions should only be used if the DMA controller was synthesized (IO_DMA_EN = true).
- *
- * @see https://stnolting.github.io/neorv32/sw/files.html
  */
 
 #ifndef neorv32_dma_h
@@ -40,7 +36,6 @@ typedef volatile struct __attribute__((packed,aligned(4))) {
 enum NEORV32_DMA_CTRL_enum {
   DMA_CTRL_EN           =  0, /**< DMA control register(0) (r/w): DMA enable */
   DMA_CTRL_AUTO         =  1, /**< DMA control register(1) (r/w): Automatic trigger mode enable */
-  DMA_CTRL_FENCE        =  2, /**< DMA control register(2) (r/w): Issue FENCE downstream operation when DMA transfer is completed */
 
   DMA_CTRL_ERROR_RD     =  8, /**< DMA control register(8)  (r/-): Error during read access; SRC_BASE shows the faulting address */
   DMA_CTRL_ERROR_WR     =  9, /**< DMA control register(9)  (r/-): Error during write access; DST_BASE shows the faulting address */
@@ -103,8 +98,6 @@ enum NEORV32_DMA_STATUS_enum {
 int  neorv32_dma_available(void);
 void neorv32_dma_enable(void);
 void neorv32_dma_disable(void);
-void neorv32_dma_fence_enable(void);
-void neorv32_dma_fence_disable(void);
 void neorv32_dma_transfer(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config);
 void neorv32_dma_transfer_auto(uint32_t base_src, uint32_t base_dst, uint32_t num, uint32_t config, int firq_sel, int firq_type);
 int  neorv32_dma_status(void);

diff --git a/sw/lib/source/neorv32_dma.c b/sw/lib/source/neorv32_dma.c
@@ -1,18 +1,14 @@
 // ================================================================================ //
 // The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              //
 // Copyright (c) NEORV32 contributors.                                              //
-// Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved.                  //
+// Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  //
 // Licensed under the BSD-3-Clause license, see LICENSE for details.                //
 // SPDX-License-Identifier: BSD-3-Clause                                            //
 // ================================================================================ //
 
 /**
  * @file neorv32_wdt.c
  * @brief Direct Memory Access Controller (DMA) HW driver source file.
- *
- * @note These functions should only be used if the DMA controller was synthesized (IO_DMA_EN = true).
- *
- * @see https://stnolting.github.io/neorv32/sw/files.html
  */
 
 #include <neorv32.h>
@@ -52,25 +48,6 @@ void neorv32_dma_disable(void) {
 }
 
 
-/**********************************************************************//**
- * Enable memory barrier (fence): issue a FENCE operation when DMA transfer
- * completes  without errors.
- **************************************************************************/
-void neorv32_dma_fence_enable(void) {
-
-  NEORV32_DMA->CTRL |= (uint32_t)(1 << DMA_CTRL_FENCE);
-}
-
-
-/**********************************************************************//**
- * Disable memory barrier (fence).
- **************************************************************************/
-void neorv32_dma_fence_disable(void) {
-
-  NEORV32_DMA->CTRL &= ~((uint32_t)(1 << DMA_CTRL_FENCE));
-}
-
-
 /**********************************************************************//**
  * Trigger manual DMA transfer.
  *

diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd
@@ -412,11 +412,6 @@
               <bitRange>[1:1]</bitRange>
               <description>Enable automatic transfer trigger (FIRQ-triggered)</description>
             </field>
-            <field>
-              <name>DMA_CTRL_FENCE</name>
-              <bitRange>[2:2]</bitRange>
-              <description>Issue a downstream FENCE operation when DMA transfer completes (without errors)</description>
-            </field>
             <field>
               <name>DMA_CTRL_ERROR_RD</name>
               <bitRange>[8:8]</bitRange>