Fix decoder omission highlightedby issue #89

decoder.tex

@@ -6,7 +6,7 @@ \chapter{Decoder}
 Reference Python implementations of both the encoder and decoder can be found at 
 \href{https://github.com/riscv-non-isa/riscv-trace-spec}{https://github.com/riscv-non-isa/riscv-trace-spec}.
 
-\section{Decoder pseudo code}
+\section{Decoder pseudo code} \label{Decoder}
 
 \begin{alltt}
 # global variables
@@ -23,6 +23,7 @@ \section{Decoder pseudo code}
 global bool  start_of_trace = TRUE       # Flag indicating 1st trace packet still
                                          #   to be processed
 global       address                     # Reconstructed address from te_inst messages
+global       privilege                   # Privilege from te_inst messages
 global       options                     # Operating mode flags
 global array return_stack                # Array holding return address stack
 global       irstack_depth = 0           # Depth of the return address stack
@@ -62,6 +63,7 @@ \section{Decoder pseudo code}
       last_pc      = pc # previous pc not known but ensures correct
                         #  operation for is_sequential_jump()
 
+    privilege = te_inst.privilege
     start_of_trace = FALSE
     irstack_depth  = 0
 
@@ -117,20 +119,19 @@ \section{Decoder pseudo code}
         return
       if (stop_here)
         # Reached reported address following an uninferable discontinuity - stop here
-        if (branches > (is_branch(get_instr(pc)) ? 1 : 0))
-          # Check all branches processed (except 1 if this instruction is a branch)
+        if (unprocessed_branches(pc))
           ERROR: unprocessed branches
         return
       if (te_inst.format != 3 and pc == address and !stop_at_last_branch and
         (te_inst.notify != get_preceding_bit(te_inst, "notify")) and 
-        (branches == (is_branch(get_instr(pc)) ? 1 : 0)))
+        !unprocessed_branches(pc))
           # All branches processed, and reached reported address due to notification,
           # not as an uninferable jump target
         return
       if (te_inst.format != 3 and pc == address and !stop_at_last_branch and
         !is_uninferable_discon(get_instr(last_pc)) and 
         (te_inst.updiscon == get_preceding_bit(te_inst, "updiscon")) and 
-        (branches == (is_branch(get_instr(pc)) ? 1 : 0)) and
+        !unprocessed_branches(pc) and
         ((te_inst.irreport == get_previous_bit(te_inst, "irreport")) or 
          te_inst.irdepth == irstack_depth))
           # All branches processed, and reached reported address, but not as an
@@ -139,8 +140,8 @@ \section{Decoder pseudo code}
           #  final retired instruction
         inferred_address = TRUE
         return
-      if (te_inst.format == 3 and pc == address and
-        (branches == (is_branch(get_instr(pc)) ? 1 : 0)))
+      if (te_inst.format == 3 and pc == address and !unprocessed_branches(pc) and
+        (te_inst.privilege == privilege or is_return_from_trap(get_instr(last_pc))))
         # All branches processed, and reached reported address
         return
 \end{alltt}
@@ -258,14 +259,22 @@ \section{Decoder pseudo code}
 
   return FALSE
 
-# Determine if instruction is an uninferable discontinuity #
-function is_uninferable_discon (instr)
+# Determine if instruction is a return from trap #
+function is_return_from_trap (instr)
 
-  if (is_uninferable_jump(instr) or
-      (instr.opcode == URET)      or
+  if ((instr.opcode == URET)      or
       (instr.opcode == SRET)      or
       (instr.opcode == MRET)      or
-      (instr.opcode == DRET)      or
+      (instr.opcode == DRET))
+    return TRUE
+
+  return FALSE
+
+# Determine if instruction is an uninferrable discontinuity #
+function is_uninferrable_discon (instr)
+
+  if (is_uninferrable_jump(instr) or
+      is_return_from_trap (instr) or
       (instr.opcode == ECALL)     or
       (instr.opcode == EBREAK)    or
       (instr.opcode == C.EBREAK))
@@ -333,6 +342,13 @@ \section{Decoder pseudo code}
     return (irstack_depth > 0)
 
   return FALSE
+
+# Check for unprocessed branches #
+function unprocessed_branches (address)
+
+  # Check all branches processed (except 1 if this instruction is a branch)
+  return (branches != (is_branch(get_instr(address)) ? 1 : 0))
+
 \end{alltt}
 
 \pagebreak

riscv-trace-spec.tex

@@ -89,7 +89,8 @@ \chapter{Change History}
     \href{https://github.com/riscv-non-isa/tg-nexus-trace/blob/master/docs/RISC-V-Trace-Control-Interface.adoc}{RISC-V Trace Control Interface Specification} \newline
     - Added detail on handling of multi-load/store instructions for data trace to section \ref{sec:DataInterfaceRequirements}. \newline
     - Removed references to tail-calls in jump classifications in section \ref{sec:InstructionInterfaceRequirements}. \newline
-    - Corrected typos where \textbf{lrid} was inadvertently refered to by an earlier name (\textbf{index}) in section \ref{sec:data-loadstore}.\\
+    - Corrected typos where \textbf{lrid} was inadvertently refered to by an earlier name (\textbf{index}) in section \ref{sec:data-loadstore}. \newline
+    - Corrected reference decoder in section \ref{Decoder} to cover a corner-case related to trap returns. \\
     \hline
   \end{tabulary}
 \end{table}