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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.5k 242

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

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  3. riscv-arch-test riscv-arch-test Public

    Assembly 536 217

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 375 95

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 305 91

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 170 50

Repositories

Showing 10 of 35 repositories
  • riscv-brs Public

    The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

    riscv-non-isa/riscv-brs’s past year of commit activity
    TeX 45 CC-BY-4.0 15 20 1 Updated Feb 7, 2025
  • riscv-arch-test Public
    riscv-non-isa/riscv-arch-test’s past year of commit activity
    Assembly 536 Apache-2.0 217 49 40 Updated Feb 6, 2025
  • rvv-intrinsic-doc Public
    riscv-non-isa/rvv-intrinsic-doc’s past year of commit activity
    C 305 BSD-3-Clause 91 20 4 Updated Feb 5, 2025
  • riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    riscv-non-isa/riscv-asm-manual’s past year of commit activity
    Makefile 1,477 CC-BY-4.0 242 6 8 Updated Feb 5, 2025
  • riscv-external-debug-security Public

    The RISC-V External Debug Security Specification

    riscv-non-isa/riscv-external-debug-security’s past year of commit activity
    Makefile 19 CC-BY-4.0 4 1 0 Updated Feb 5, 2025
  • riscv-server-platform Public

    The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.

    riscv-non-isa/riscv-server-platform’s past year of commit activity
    Makefile 10 CC-BY-4.0 5 9 1 Updated Feb 3, 2025
  • riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    riscv-non-isa/riscv-sbi-doc’s past year of commit activity
    Makefile 375 CC-BY-4.0 95 14 4 Updated Feb 3, 2025
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec’s past year of commit activity
    C 170 CC-BY-4.0 50 26 19 Updated Jan 31, 2025
  • riscv-security-model Public

    RISC-V Security Model

    riscv-non-isa/riscv-security-model’s past year of commit activity
    Makefile 29 CC-BY-4.0 15 4 1 Updated Jan 28, 2025
  • riscv-ras-eri Public

    The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and confi…

    riscv-non-isa/riscv-ras-eri’s past year of commit activity
    TeX 9 CC-BY-4.0 5 0 0 Updated Jan 25, 2025
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