Add Randomization Logic to Generated Memories

lib/Conversion/SeqToSV/SeqToSV.cpp

@@ -81,7 +81,6 @@ struct ModuleLoweringState {
 
   struct FragmentInfo {
     bool needsRegFragment = false;
-    bool needsMemFragment = false;
   } fragment;
 
   HWModuleOp module;
@@ -591,9 +590,11 @@ void SeqToSVPass::runOnOperation() {
   // Identify memories and group them by module.
   auto uniqueMems = memLowering.collectMemories(modules);
   MapVector<HWModuleOp, SmallVector<FirMemLowering::MemoryConfig>> memsByModule;
+  SmallVector<HWModuleGeneratedOp> generatedModules;
   for (auto &[config, memOps] : uniqueMems) {
     // Create the `HWModuleGeneratedOp`s for each unique configuration.
     auto genOp = memLowering.createMemoryModule(config, memOps);
+    generatedModules.push_back(genOp);
 
     // Group memories by their parent module for parallelism.
     for (auto memOp : memOps) {
@@ -630,10 +631,10 @@ void SeqToSVPass::runOnOperation() {
 
         if (auto *it = memsByModule.find(module); it != memsByModule.end()) {
           memLowering.lowerMemoriesInModule(module, it->second);
-          if (!disableMemRandomization) {
-            state.fragment.needsMemFragment = true;
-          }
+          // Generated memories need register randomization since `HWMemSimImpl`
+          // may add registers.
           needsMemRandomization = true;
+          needsRegRandomization = true;
         }
         return state.immutableValueLowering.lower();
       });
@@ -650,8 +651,8 @@ void SeqToSVPass::runOnOperation() {
 
   for (auto &[_, state] : moduleLoweringStates) {
     const auto &info = state.fragment;
-    if (!info.needsRegFragment && !info.needsMemFragment) {
-      // If neither is emitted, just skip it.
+    // Do not add fragments if not needed.
+    if (!info.needsRegFragment) {
       continue;
     }
 
@@ -661,16 +662,28 @@ void SeqToSVPass::runOnOperation() {
             module->getAttrOfType<ArrayAttr>(emit::getFragmentsAttrName()))
       fragmentAttrs = llvm::to_vector(others);
 
-    if (info.needsRegFragment)
+    if (info.needsRegFragment) {
       fragmentAttrs.push_back(randomInitRegFragmentName);
-    if (info.needsMemFragment)
-      fragmentAttrs.push_back(randomInitMemFragmentName);
-    fragmentAttrs.push_back(randomInitFragmentName);
+      fragmentAttrs.push_back(randomInitFragmentName);
+    }
 
     module->setAttr(emit::getFragmentsAttrName(),
                     ArrayAttr::get(context, fragmentAttrs));
   }
 
+  // Set fragments for generated modules.
+  SmallVector<Attribute> genModFragments;
+  if (!disableRegRandomization)
+    genModFragments.push_back(randomInitRegFragmentName);
+  if (!disableMemRandomization)
+    genModFragments.push_back(randomInitMemFragmentName);
+  if (!genModFragments.empty()) {
+    genModFragments.push_back(randomInitFragmentName);
+    auto fragmentAttr = ArrayAttr::get(context, genModFragments);
+    for (auto genOp : generatedModules)
+      genOp->setAttr(emit::getFragmentsAttrName(), fragmentAttr);
+  }
+
   // Mark all ops which can have clock types as illegal.
   SeqToSVTypeConverter typeConverter;
   ConversionTarget target(*context);

lib/Dialect/Seq/Transforms/HWMemSimImpl.cpp

@@ -753,6 +753,8 @@ void HWMemSimImplPass::runOnOperation() {
                      addVivadoRAMAddressConflictSynthesisBugWorkaround,
                      mlirModuleNamespace)
             .generateMemory(newModule, mem);
+        if (auto fragments = oldModule->getAttr(emit::getFragmentsAttrName()))
+          newModule->setAttr(emit::getFragmentsAttrName(), fragments);
       }
 
       oldModule.erase();

test/Conversion/SeqToSV/header.mlir

@@ -68,8 +68,11 @@
 
 emit.fragment @SomeFragment {}
 
+// CHECK-LABEL: hw.module.generated
+// CHECK-SAME:    emit.fragments = [@RANDOM_INIT_REG_FRAGMENT, @RANDOM_INIT_MEM_FRAGMENT, @RANDOM_INIT_FRAGMENT]
+
 // CHECK-LABEL: hw.module @fragment_ref(in %clk : i1)
-// CHECK-SAME: emit.fragments = [@SomeFragment, @RANDOM_INIT_REG_FRAGMENT, @RANDOM_INIT_MEM_FRAGMENT, @RANDOM_INIT_FRAGMENT]
+// CHECK-SAME: emit.fragments = [@SomeFragment, @RANDOM_INIT_REG_FRAGMENT, @RANDOM_INIT_FRAGMENT]
 hw.module @fragment_ref(in %clk : !seq.clock) attributes {emit.fragments = [@SomeFragment]} {
   %cst0_i32 = hw.constant 0 : i32
   %rA = seq.firreg %cst0_i32 clock %clk sym @regA : i32

test/Dialect/Seq/hw-memsim.mlir

@@ -445,3 +445,29 @@ hw.module.generated @ReadWriteWithHighWriteLatency, @FIRRTLMem(in %rw_addr: i4,
 // CHECK: [[TMP:%.+]] = comb.and [[WRITE_WMODE_3R]], %true
 // CHECK: [[WCOND:%.+]] comb.and [[WRITE_EN_3R]], [[TMP]]
 // CHECK: [[WPTR:%.+]] = sv.array_index_inout [[MEM]][[[WRITE_ADDR_3R]]]
+
+emit.fragment @Fragment {}
+hw.module.generated @TestFragment, @FIRRTLMem(
+  in %ro_addr_0: i4,
+  in %ro_en_0: i1,
+  in %ro_clock_0: i1,
+  out ro_data_0: i16
+) attributes {
+  depth = 10 : i64,
+  numReadPorts = 1 : ui32,
+  numReadWritePorts = 0 : ui32,
+  numWritePorts = 0 : ui32,
+  readLatency = 0 : ui32,
+  readUnderWrite = 0 : i32,
+  width = 16 : ui32,
+  writeClockIDs = [],
+  writeLatency = 1 : ui32,
+  writeUnderWrite = 0 : i32,
+  initFilename = "",
+  initIsBinary = false,
+  initIsInline = false,
+  emit.fragments = [@Fragment]
+}
+
+// CHECK-LABEL: hw.module private @TestFragment
+// CHECK-SAME:    emit.fragments = [@Fragment]