Patch RT1060x registers

devices/common_patches/enc.yaml

@@ -0,0 +1,9 @@
+# Add FILT_PRSC to ENCx FILT registers
+ENC*:
+  FILT:
+    _add:
+      FILT_PRSC:
+        description: Clock prescaler value
+        bitOffset: 13
+        bitWidth: 3
+        access: read-write

devices/common_patches/flexspi.yaml

@@ -0,0 +1,18 @@
+# Add SERCLKDIV to FLEXSPIx MCR0 registers
+FLEXSPI*:
+  MCR0:
+    _add:
+      SERCLKDIV:
+        description: serial root clock divisor
+        bitOffset: 8
+        bitWidth: 3
+        access: read-write
+    SERCLKDIV:
+      SERCLKDIV_0: [0b000, "Divided by 1"]
+      SERCLKDIV_1: [0b001, "Divided by 2"]
+      SERCLKDIV_2: [0b010, "Divided by 3"]
+      SERCLKDIV_3: [0b011, "Divided by 4"]
+      SERCLKDIV_4: [0b100, "Divided by 5"]
+      SERCLKDIV_5: [0b101, "Divided by 6"]
+      SERCLKDIV_6: [0b110, "Divided by 7"]
+      SERCLKDIV_7: [0b111, "Divided by 8"]

devices/imxrt1015.yaml

@@ -8,6 +8,8 @@ _include:
   - "common_patches/lpuart_ridmae.yaml"
   - "common_patches/pit.yaml"
   - "common_patches/xbara.yaml"
+  - "common_patches/enc.yaml"
+  - "common_patches/flexspi.yaml"
 
 # See rationale in imxrt1011.yaml
 _modify:

devices/imxrt1021.yaml

@@ -8,6 +8,8 @@ _include:
   - "common_patches/lpuart_ridmae.yaml"
   - "common_patches/pit.yaml"
   - "common_patches/xbara.yaml"
+  - "common_patches/enc.yaml"
+  - "common_patches/flexspi.yaml"
 
 # See rationale in imxrt1011.yaml
 _modify:

devices/imxrt1051.yaml

@@ -1,8 +1,10 @@
 _svd: "../svd/imxrt1051.svd"
 
-_include: 
+_include:
   - "common.yaml"
   - "common_patches/pwm1/submodule_cluster.yaml"
   - "common_patches/usb1.yaml"
   - "common_patches/dma0/tcd_cluster.yaml"
   - "common_patches/xbara.yaml"
+  - "common_patches/flexspi.yaml"
+  - "common_patches/enc.yaml"

devices/imxrt1052.yaml

@@ -1,8 +1,10 @@
 _svd: "../svd/imxrt1052.svd"
 
-_include: 
+_include:
   - "common.yaml"
   - "common_patches/pwm1/submodule_cluster.yaml"
   - "common_patches/usb1.yaml"
   - "common_patches/dma0/tcd_cluster.yaml"
   - "common_patches/xbara.yaml"
+  - "common_patches/flexspi.yaml"
+  - "common_patches/enc.yaml"

devices/imxrt1061.yaml

@@ -8,3 +8,5 @@ _include:
   - "common_patches/xbara.yaml"
   - "common_patches/instance_renames.yaml"
   - "common_patches/flexio_106x.yaml"
+  - "common_patches/enc.yaml"
+  - "common_patches/flexspi.yaml"

devices/imxrt1062.yaml

@@ -8,3 +8,5 @@ _include:
   - "common_patches/xbara.yaml"
   - "common_patches/instance_renames.yaml"
   - "common_patches/flexio_106x.yaml"
+  - "common_patches/enc.yaml"
+  - "common_patches/flexspi.yaml"

devices/imxrt1064.yaml

@@ -8,3 +8,5 @@ _include:
   - "common_patches/xbara.yaml"
   - "common_patches/instance_renames.yaml"
   - "common_patches/flexio_106x.yaml"
+  - "common_patches/enc.yaml"
+  - "common_patches/flexspi.yaml"

src/blocks/imxrt1015/enc1.rs

@@ -271,6 +271,14 @@ pub mod FILT {
         pub mod W {}
         pub mod RW {}
     }
+    #[doc = "Clock prescaler value"]
+    pub mod FILT_PRSC {
+        pub const offset: u16 = 13;
+        pub const mask: u16 = 0x07 << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {}
+    }
 }
 #[doc = "Watchdog Timeout Register"]
 pub mod WTR {

src/blocks/imxrt1015/flexspi.rs

@@ -136,6 +136,31 @@ pub mod MCR0 {
             pub const ATDFEN_1: u32 = 0x01;
         }
     }
+    #[doc = "The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking."]
+    pub mod SERCLKDIV {
+        pub const offset: u32 = 8;
+        pub const mask: u32 = 0x07 << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {
+            #[doc = "Divided by 1"]
+            pub const SERCLKDIV_0: u32 = 0;
+            #[doc = "Divided by 2"]
+            pub const SERCLKDIV_1: u32 = 0x01;
+            #[doc = "Divided by 3"]
+            pub const SERCLKDIV_2: u32 = 0x02;
+            #[doc = "Divided by 4"]
+            pub const SERCLKDIV_3: u32 = 0x03;
+            #[doc = "Divided by 5"]
+            pub const SERCLKDIV_4: u32 = 0x04;
+            #[doc = "Divided by 6"]
+            pub const SERCLKDIV_5: u32 = 0x05;
+            #[doc = "Divided by 7"]
+            pub const SERCLKDIV_6: u32 = 0x06;
+            #[doc = "Divided by 8"]
+            pub const SERCLKDIV_7: u32 = 0x07;
+        }
+    }
     #[doc = "Half Speed Serial Flash access Enable."]
     pub mod HSEN {
         pub const offset: u32 = 11;
@@ -162,7 +187,7 @@ pub mod MCR0 {
             pub const DOZEEN_1: u32 = 0x01;
         }
     }
-    #[doc = "This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA\\[3:0\\] and SIOB\\[3:0\\])."]
+    #[doc = "This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA\\[3:0\\] and B_DATA\\[3:0\\])."]
     pub mod COMBINATIONEN {
         pub const offset: u32 = 13;
         pub const mask: u32 = 0x01 << offset;
@@ -175,7 +200,7 @@ pub mod MCR0 {
             pub const COMBINATIONEN_1: u32 = 0x01;
         }
     }
-    #[doc = "This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0\\[RXCLKSRC\\]=2)."]
+    #[doc = "This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0\\[RXCLKSRC\\]=2)."]
     pub mod SCKFREERUNEN {
         pub const offset: u32 = 14;
         pub const mask: u32 = 0x01 << offset;

src/blocks/imxrt1021/enc.rs

@@ -271,6 +271,14 @@ pub mod FILT {
         pub mod W {}
         pub mod RW {}
     }
+    #[doc = "Clock prescaler value"]
+    pub mod FILT_PRSC {
+        pub const offset: u16 = 13;
+        pub const mask: u16 = 0x07 << offset;
+        pub mod R {}
+        pub mod W {}
+        pub mod RW {}
+    }
 }
 #[doc = "Watchdog Timeout Register"]
 pub mod WTR {