fix compile for chisel5

1. remove Cat from util chipsalliance/chisel#3062 2. remove experimental.IO chipsalliance/chisel#2863
chipsalliance · Mar 9, 2023 · 743e06f · 743e06f
1 parent b2fd991
commit 743e06f
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Showing 23 changed files with 20 additions and 24 deletions.
diff --git a/src/main/scala/amba/axi4/Deinterleaver.scala b/src/main/scala/amba/axi4/Deinterleaver.scala
@@ -3,8 +3,7 @@
 package freechips.rocketchip.amba.axi4
 
 import chisel3._
-import chisel3.util.{Cat, isPow2, log2Ceil, ReadyValidIO,
-  log2Up, OHToUInt, Queue, QueueIO, UIntToOH}
+import chisel3.util.{isPow2, log2Ceil, ReadyValidIO, log2Up, OHToUInt, Queue, QueueIO, UIntToOH}
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util.leftOR

diff --git a/src/main/scala/amba/axi4/IdIndexer.scala b/src/main/scala/amba/axi4/IdIndexer.scala
@@ -6,7 +6,7 @@ import chisel3._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
-import chisel3.util.{log2Ceil, Cat}
+import chisel3.util.log2Ceil
 import freechips.rocketchip.util.EnhancedChisel3Assign
 
 case object AXI4ExtraId extends ControlKey[UInt]("extra_id")

diff --git a/src/main/scala/diplomacy/Nodes.scala b/src/main/scala/diplomacy/Nodes.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.diplomacy
 
 import Chisel._
-import chisel3.experimental.IO
 import chisel3.internal.sourceinfo.SourceInfo
 import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.util.HeterogeneousBag

diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala
@@ -20,7 +20,7 @@
 package freechips.rocketchip.groundtest
 
 import chisel3._
-import chisel3.util.{log2Up, MuxLookup, Cat, log2Ceil, Enum}
+import chisel3.util.{log2Up, MuxLookup, log2Ceil, Enum}
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.diplomacy.{ClockCrossingType}
 import freechips.rocketchip.rocket._

diff --git a/src/main/scala/jtag/JtagShifter.scala b/src/main/scala/jtag/JtagShifter.scala
@@ -5,7 +5,7 @@ package freechips.rocketchip.jtag
 import chisel3._
 import chisel3.experimental.DataMirror
 import chisel3.internal.firrtl.KnownWidth
-import chisel3.util.{Cat, Valid}
+import chisel3.util.Valid
 
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.property

diff --git a/src/main/scala/regmapper/RegMapper.scala b/src/main/scala/regmapper/RegMapper.scala
@@ -4,7 +4,7 @@ package freechips.rocketchip.regmapper
 
 import chisel3._
 import chisel3.internal.sourceinfo.SourceInfo
-import chisel3.util.{DecoupledIO, Decoupled, Queue, Cat, FillInterleaved, UIntToOH}
+import chisel3.util.{DecoupledIO, Decoupled, Queue, FillInterleaved, UIntToOH}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
 import freechips.rocketchip.util.property

diff --git a/src/main/scala/regmapper/Test.scala b/src/main/scala/regmapper/Test.scala
@@ -3,7 +3,7 @@
 package freechips.rocketchip.regmapper
 
 import chisel3._
-import chisel3.util.{Cat, log2Ceil}
+import chisel3.util.log2Ceil
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy.LazyModuleImp
 import freechips.rocketchip.util.{Pow2ClockDivider}

diff --git a/src/main/scala/rocket/ALU.scala b/src/main/scala/rocket/ALU.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{BitPat, Fill, Cat, Reverse}
+import chisel3.util.{BitPat, Fill, Reverse}
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tile.CoreModule
 

diff --git a/src/main/scala/rocket/Breakpoint.scala b/src/main/scala/rocket/Breakpoint.scala
@@ -3,7 +3,6 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Cat}
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
 import freechips.rocketchip.util._

diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}
+import chisel3.util.{BitPat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.debug.DebugModuleKey
 import freechips.rocketchip.tile._

diff --git a/src/main/scala/rocket/HellaCacheArbiter.scala b/src/main/scala/rocket/HellaCacheArbiter.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Cat,log2Up}
+import chisel3.util.log2Up
 import org.chipsalliance.cde.config.Parameters
 
 class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module

diff --git a/src/main/scala/rocket/IBuf.scala b/src/main/scala/rocket/IBuf.scala
@@ -3,7 +3,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Decoupled,log2Ceil,Cat,UIntToOH,Fill}
+import chisel3.util.{Decoupled,log2Ceil,UIntToOH,Fill}
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._

diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Cat, Decoupled, Mux1H, OHToUInt, RegEnable, Valid, isPow2, log2Ceil, log2Up, PopCount}
+import chisel3.util.{Decoupled, Mux1H, OHToUInt, RegEnable, Valid, isPow2, log2Ceil, log2Up, PopCount}
 import freechips.rocketchip.amba._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._

diff --git a/src/main/scala/rocket/Multiplier.scala b/src/main/scala/rocket/Multiplier.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Cat, log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
+import chisel3.util.{log2Up, log2Ceil, log2Floor, Log2, Decoupled, Enum, Fill, Valid, Pipe}
 import freechips.rocketchip.util._
 
 class MultiplierReq(dataBits: Int, tagBits: Int, aluFn: ALUFN = new ALUFN) extends Bundle {

diff --git a/src/main/scala/rocket/PMP.scala b/src/main/scala/rocket/PMP.scala
@@ -3,7 +3,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Cat, log2Ceil}
+import chisel3.util.log2Ceil
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._

diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
+import chisel3.util.{Arbiter, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch}
 import chisel3.withClock
 import chisel3.internal.sourceinfo.SourceInfo
 import org.chipsalliance.cde.config.Parameters

diff --git a/src/main/scala/rocket/SimpleHellaCacheIF.scala b/src/main/scala/rocket/SimpleHellaCacheIF.scala
@@ -4,7 +4,7 @@
 package freechips.rocketchip.rocket
 
 import chisel3._
-import chisel3.util.{Valid,Decoupled,Queue,log2Up,OHToUInt,UIntToOH,PriorityEncoderOH,Arbiter,RegEnable,Cat}
+import chisel3.util.{Valid,Decoupled,Queue,log2Up,OHToUInt,UIntToOH,PriorityEncoderOH,Arbiter,RegEnable}
 
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util._

diff --git a/src/main/scala/tilelink/AtomicAutomata.scala b/src/main/scala/tilelink/AtomicAutomata.scala
@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
 import scala.math.{min,max}
-import chisel3.util.{PriorityMux, Cat, FillInterleaved, Mux1H, MuxLookup, log2Up}
+import chisel3.util.{PriorityMux, FillInterleaved, Mux1H, MuxLookup, log2Up}
 
 // Ensures that all downstream RW managers support Atomic operations.
 // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.

diff --git a/src/main/scala/tilelink/ToAHB.scala b/src/main/scala/tilelink/ToAHB.scala
@@ -9,7 +9,7 @@ import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
 import AHBParameters._
-import chisel3.util.{RegEnable, Queue, Cat, log2Ceil}
+import chisel3.util.{RegEnable, Queue, log2Ceil}
 import freechips.rocketchip.util.EnhancedChisel3Assign
 
 case class TLToAHBNode(supportHints: Boolean)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AHBImpMaster)(

diff --git a/src/main/scala/tilelink/ToAXI4.scala b/src/main/scala/tilelink/ToAXI4.scala
@@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.amba._
-import chisel3.util.{log2Ceil, UIntToOH, Queue, Decoupled, Cat}
+import chisel3.util.{log2Ceil, UIntToOH, Queue, Decoupled}
 import freechips.rocketchip.util.EnhancedChisel3Assign
 
 class AXI4TLStateBundle(val sourceBits: Int) extends Bundle {

diff --git a/src/main/scala/tilelink/WidthWidget.scala b/src/main/scala/tilelink/WidthWidget.scala
@@ -3,7 +3,7 @@
 package freechips.rocketchip.tilelink
 
 import chisel3._
-import chisel3.util.{DecoupledIO, log2Ceil, Cat, RegEnable}
+import chisel3.util.{DecoupledIO, log2Ceil, RegEnable}
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.util._

diff --git a/src/main/scala/unittest/UnitTest.scala b/src/main/scala/unittest/UnitTest.scala
@@ -4,7 +4,6 @@ package freechips.rocketchip.unittest
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{IO}
 import org.chipsalliance.cde.config._
 import freechips.rocketchip.util._
 

diff --git a/src/main/scala/util/SynchronizerReg.scala b/src/main/scala/util/SynchronizerReg.scala
@@ -3,7 +3,7 @@
 package freechips.rocketchip.util
 
 import chisel3._
-import chisel3.util.{RegEnable, Cat}
+import chisel3.util.RegEnable
 
 /**  These wrap behavioral
   *  shift and next registers into specific modules to allow for