Make CheckWidths accept zero-width UIntLiterals

[jackkoenig]

Fixes #508

Release notes:
Zero-width literals with value zero are now allowed.

[aswaterman]

lgtm

[azidar]

shouldn't you check if x is assigned to be zero?

[jackkoenig]

This diff is messed up, this check for this test is identical to the one above so git strangely put the new code in the middle, but if you look below there is more to the new test.

[azidar]

Yeah, that's super weird, if I view the whole file it looks fine.

[jackkoenig]

This change seems to lead to a zero-width Vec issue in the Chisel tests. Looking into it

[jackkoenig]

(Well I think this one combined with the one where Chisel emits zero width UInts)

[donggyukim]

@colinschmidt Can you confirm this works?

[jackkoenig]

Here's the Chisel branch, looking in to the Chisel test failure: https://github.com/ucb-bar/chisel3/tree/one-entry-enum

[colinschmidt]

Thanks @jackkoenig I'll test with that branch and this firrtl branch

[colinschmidt]

Hmm I got a bunch of these errors:

======== Starting Transform CheckWidths$ ========
[error] (run-main-0) firrtl.passes.PassExceptions:
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module FinishQueue] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module FinishQueue_1] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module FinishQueue_2] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module Queue_16] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module Queue_17] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module Queue_127] Parameter 1 in tail operator is larger than input width 1.

[jackkoenig]

It seems like there might be some hidden zero-width wire problems in Firrtl, perhaps we should just patch Chisel by not emitting zero-width for 1-entry Enums and at least fix THAT problem

[jackkoenig]

I added a testcase that currently fails so that a fix for it (and possibly other issues) can accompany this change.

[azidar]

Any updates on this? Is this dated?

[jackkoenig]

No updates, I think it's a lingering problem

[ucbjrl]

All tests (FIRRTL) currently pass. I'm running regression tests with the rest of the BIG6.

[chick]

This looks ok to me (weird diff not withstanding)
Should get branch updated

[albert-magyar]

I rebased and cleaned up. The previously failing Vec test works now; should we consider merging this now @jackkoenig?