WireDefault instead of WireInit, keep WireInit around

[schoeberl]

Type of change: feature request

Impact: API modification

Development Phase: implementation

Release Notes

Rename WireInit to WireDefault as its semantic is not an initialization (like a register on a reset), but a default assignment for a combinational circuit.

WireInit is kept around as an alias to WireDefault.

Closes #959

[ducky64]

Related issue #959, where there's been some discussion on this

[schoeberl]

closes #959

[edwardcwang]

This seems to correspond with what was agreed to at the January 25, 2019 meeting

[schoeberl]

anyone with write access to Chisel3 will do the merge?

[schoeberl]

Thanks :-) Martin

…

On 25 Jan, 2019, at 23:24, Richard Lin ***@***.***> wrote: Merged #986 <#986> into master. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#986 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AAntmCQK3tOUQeB_2aYosOk7VbUfQDhDks5vHAKTgaJpZM4aER6->.

[ucbjrl]

This breaks rocket-chip which tries to refer to chisel3.core.WireInit:

[info] Compiling 280 Scala sources to /vm/home/jenkins/sharedspace/mc-rocket-chip/repo/target/scala-2.12/classes ...
[error] /vm/home/jenkins/sharedspace/mc-rocket-chip/repo/src/main/scala/rocket/DCache.scala:13:8: object WireInit is not a member of package chisel3.core
[error] import chisel3.core.{DontCare, WireInit}
[error]        ^
[error] /vm/home/jenkins/sharedspace/mc-rocket-chip/repo/src/main/scala/rocket/DCache.scala:177:22: not found: value WireInit
[error]   val uncachedResp = WireInit(new HellaCacheReq, DontCare)
[error]                      ^

[ducky64]

#1006 is probably the actual underlying issue, we really didn't design for people importing chisel3.core.

[edwardcwang]

chipsalliance/rocket-chip#1827