[chisel5] git subtree add FIRRTL #2982
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* Optionally defines read-under-write behavior for all 'undefined' memories * Use DefaultReadFirstAnnotation to choose read-first default * Use DefaultWriteFirstAnnotation to choose write-first default * Seal DefaultReadUnderWriteAnnotation based on Jack's feedback
* Update test to include both 'old' and 'new' read-under-write values
* Address @ekiwi comments from review * Change match cases to scalafmt-mandated lined-up style
* Update name of FPGA flag based on Jack's comment * Add Scaladoc to describe what each constituent transform does * Add SeparateWriteClocks to --target:fpga
Add -fpga flag to enable FPGA-oriented compilation strategies (currently for memories)
To maintain binary compatibility, InlineAcrossCasts is just aliases to the now deprecated InlineCasts. We can make the binary incompatible change of renaming the class and object for 1.5. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
* bitWidth: add scaladoc * smt: use existing bitWidth API
Using Utils.indent() gives deprecation warnings to use Serializer instead. However, the Serializer class itself doesn't provide a means to manually indent a FirrtlNode string a certain number of times. The indent variable, previously hardcoded to 0, is now exposed as a second parameter for the modified serialize function, and the old serialize function just calls the modified serialize with indents = 0 for binary compatibility Co-authored-by: Megan Wachs <[email protected]>
Also make minor updates to CI workflow
Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:
circuit Foo :
module Foo :
input a: UInt<3>
output b: UInt<4>
b <= asUInt(xor(asSInt(a), SInt<4>(0)))
This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.
This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.
With Stage/Phase, users can provide complex functionality at the phase level rather than just the transform level. It is useful to have the same logging information at that level. Note that this change still logs transforms in the same way, but now the time in inclusive of annotation renaming which can also [unfortunately] be slow. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: jackkoenig <[email protected]>
Looks like a typo/auto-merge hiccup.
* remove all deprecations, switch to new API. * Add MemLibOutConfigFileAnnotation to replace ConfWriter. * Inline CreateMemoryAnnotations in ReplSeqMem. * Dont use ConfWriter anymore. * Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation. * Fix for review. 0. Since DependencyAPI only initiate transform only once, ListBuffer is dangerous to use, remove defAnnotatedMemories from Transform. 1. Add trait HasAnnotatedMemories to store ListBuffer, MemLibOutConfigFileAnnotation also extends from which now. * Use two annotations converting and storing DefMemory. 0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation creating PinAnnotation. 1. add DumpMemoryAnnotations to convert from AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation 2. refactor MemLibOutConfigFileAnnotation and remove HasAnnotatedMemories 3. add private AnnotatedMemoriesCollectorAnnotation to store mutable DefAnnotatedMemory 4. change ReplSeqMem to SeqTransform * Fix for review. 0. replace AnnotatedMemoriesCollectorAnnotation with immutable AnnotatedMemoriesAnnotation. 1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute. * private functions in ReplaceMemMacros transform. * scalafmt * remove ConfWriter API.
Co-authored-by: Jiuyang Liu <[email protected]>
Co-authored-by: Jiuyang Liu <[email protected]>
Co-authored-by: Jiuyang Liu <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Jiuyang Liu <[email protected]>
Co-authored-by: Jiuyang Liu <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: Jiuyang Liu <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> Co-authored-by: Jiuyang Liu <[email protected]>
Co-authored-by: Jiuyang Liu <[email protected]> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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- Use regular expressions to get version strings more rigorously - Add version discriminant function, you can compare version size - Correct the version comparison of antlr under special conditions - Improve the version comparison of protoc Signed-off-by: Huang Rui <[email protected]>
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jackkoenig
approved these changes
Feb 28, 2023
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Move the FIRRTL repository in-tree. This is done in preparation for the upcoming Chisel 5 release. For more information on this, refer to the
ROADMAP.md.This is a draft until the Chisel 3.6 release is out. I will keep this and dependent PRs up-to-date until this release happens.
To update this, I find it easiest to just redo the operation that added the subtree:
Also, this is a patch that is broken out of @azidar's original
chisel5branch in order to make later changes more easily reviewable. (This patch only does thegit subtree addand nothing else.)