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Create board-nanopi-r3s-fix-leds.patch
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patch/kernel/archive/rockchip64-6.13/board-nanopi-r3s-fix-leds.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 | ||
From: John Doe <[email protected]> | ||
Date: Mon, 27 Jan 2025 14:11:28 +0000 | ||
Subject: Patching kernel rockchip64 files | ||
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | ||
drivers/net/ethernet/realtek/r8169_main.c drivers/net/phy/realtek.c | ||
|
||
Signed-off-by: John Doe <[email protected]> | ||
--- | ||
arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 42 +++++++--- | ||
drivers/net/ethernet/realtek/r8169_main.c | 11 +++ | ||
drivers/net/phy/realtek.c | 11 +++ | ||
3 files changed, 54 insertions(+), 10 deletions(-) | ||
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||
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | ||
index fb1f65c86..4589ed45b 100644 | ||
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | ||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | ||
@@ -51,21 +51,24 @@ gpio-leds { | ||
power_led: led-0 { | ||
color = <LED_COLOR_ID_RED>; | ||
function = LED_FUNCTION_POWER; | ||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; | ||
default-state = "on"; | ||
+ linux,default-trigger = "heartbeat"; | ||
}; | ||
|
||
lan_led: led-1 { | ||
color = <LED_COLOR_ID_GREEN>; | ||
function = LED_FUNCTION_LAN; | ||
+ function-enumerator = <2>; | ||
gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; | ||
}; | ||
|
||
wan_led: led-2 { | ||
color = <LED_COLOR_ID_GREEN>; | ||
function = LED_FUNCTION_WAN; | ||
+ function-enumerator = <3>; | ||
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; | ||
}; | ||
}; | ||
|
||
vcc3v3_sys: regulator-vcc3v3-sys { | ||
@@ -135,22 +138,31 @@ &cpu2 { | ||
&cpu3 { | ||
cpu-supply = <&vdd_cpu>; | ||
}; | ||
|
||
&gmac1 { | ||
+ phy-mode = "rgmii"; | ||
+ clock_in_out = "output"; | ||
+ | ||
+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; | ||
+ snps,reset-active-low; | ||
+ /* Reset time is 15ms, 50ms for rtl8211f */ | ||
+ snps,reset-delays-us = <0 15000 50000>; | ||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; | ||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; | ||
assigned-clock-rates = <0>, <125000000>; | ||
- clock_in_out = "output"; | ||
- phy-mode = "rgmii-id"; | ||
- phy-handle = <&rgmii_phy1>; | ||
+ | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&gmac1m0_miim | ||
&gmac1m0_tx_bus2_level3 | ||
&gmac1m0_rx_bus2 | ||
&gmac1m0_rgmii_clk_level2 | ||
&gmac1m0_rgmii_bus_level3>; | ||
+ tx_delay = <0x3c>; | ||
+ rx_delay = <0x2f>; | ||
+ | ||
+ phy-handle = <&rgmii_phy1>; | ||
status = "okay"; | ||
}; | ||
|
||
&gpu { | ||
mali-supply = <&vdd_gpu>; | ||
@@ -403,25 +415,35 @@ hym8563: rtc@51 { | ||
}; | ||
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||
&mdio1 { | ||
rgmii_phy1: ethernet-phy@1 { | ||
compatible = "ethernet-phy-ieee802.3-c22"; | ||
- reg = <1>; | ||
+ reg = <0x1>; | ||
interrupt-parent = <&gpio4>; | ||
interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>; | ||
pinctrl-names = "default"; | ||
- pinctrl-0 = <ð_phy_reset_pin>; | ||
- reset-assert-us = <20000>; | ||
- reset-deassert-us = <100000>; | ||
- reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; | ||
+ pinctrl-0 = <&gmac_int>; | ||
+ realtek,ledsel = <0xae00>; | ||
}; | ||
}; | ||
|
||
&pcie2x1 { | ||
pinctrl-names = "default"; | ||
pinctrl-0 = <&pcie_reset_h>; | ||
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; | ||
+ | ||
+ pcie@0,0 { | ||
+ reg = <0x00000000 0 0 0 0>; | ||
+ #address-cells = <3>; | ||
+ #size-cells = <2>; | ||
+ | ||
+ r8169: pcie@1,0 { | ||
+ reg = <0x000000 0 0 0 0>; | ||
+ local-mac-address = [ 00 00 00 00 00 00 ]; | ||
+ realtek,ledsel = <0x870>; | ||
+ }; | ||
+ }; | ||
status = "okay"; | ||
}; | ||
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||
&pinctrl { | ||
gpio-leds { | ||
@@ -437,12 +459,12 @@ wan_led_pin: wan-led-pin { | ||
rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; | ||
}; | ||
}; | ||
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||
gmac { | ||
- eth_phy_reset_pin: eth-phy-reset-pin { | ||
- rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; | ||
+ gmac_int: gmac-int { | ||
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; | ||
}; | ||
}; | ||
|
||
pcie { | ||
pcie_reset_h: pcie-reset-h { | ||
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c | ||
index 8a3959bb2..f8c046a69 100644 | ||
--- a/drivers/net/ethernet/realtek/r8169_main.c | ||
+++ b/drivers/net/ethernet/realtek/r8169_main.c | ||
@@ -19,10 +19,11 @@ | ||
#include <linux/phy.h> | ||
#include <linux/if_vlan.h> | ||
#include <linux/in.h> | ||
#include <linux/io.h> | ||
#include <linux/ip.h> | ||
+#include <linux/of.h> | ||
#include <linux/tcp.h> | ||
#include <linux/interrupt.h> | ||
#include <linux/dma-mapping.h> | ||
#include <linux/pm_runtime.h> | ||
#include <linux/bitfield.h> | ||
@@ -2404,10 +2405,19 @@ void r8169_apply_firmware(struct rtl8169_private *tp) | ||
!(val & BMCR_RESET), | ||
50000, 600000, true); | ||
} | ||
} | ||
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||
+static void rtl8168_led_of_init(struct rtl8169_private *tp) | ||
+{ | ||
+ struct device *d = tp_to_dev(tp); | ||
+ u32 val; | ||
+ | ||
+ if (!of_property_read_u32(d->of_node, "realtek,ledsel", &val)) | ||
+ RTL_W16(tp, LED_CTRL, val); | ||
+} | ||
+ | ||
static void rtl8168_config_eee_mac(struct rtl8169_private *tp) | ||
{ | ||
/* Adjust EEE LED frequency */ | ||
if (tp->mac_version != RTL_GIGA_MAC_VER_38) | ||
RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); | ||
@@ -3389,10 +3399,11 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) | ||
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||
rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); | ||
rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); | ||
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||
rtl8168_config_eee_mac(tp); | ||
+ rtl8168_led_of_init(tp); | ||
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||
RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); | ||
RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); | ||
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||
RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); | ||
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c | ||
index f65d7f1f3..f5d831924 100644 | ||
--- a/drivers/net/phy/realtek.c | ||
+++ b/drivers/net/phy/realtek.c | ||
@@ -121,10 +121,19 @@ static int rtl821x_read_page(struct phy_device *phydev) | ||
static int rtl821x_write_page(struct phy_device *phydev, int page) | ||
{ | ||
return __phy_write(phydev, RTL821x_PAGE_SELECT, page); | ||
} | ||
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||
+static void rtl821x_led_of_init(struct phy_device *phydev) | ||
+{ | ||
+ struct device *dev = &phydev->mdio.dev; | ||
+ u32 val; | ||
+ | ||
+ if (!of_property_read_u32(dev->of_node, "realtek,ledsel", &val)) | ||
+ phy_write_paged(phydev, 0xd04, 0x10, val); | ||
+} | ||
+ | ||
static int rtl821x_probe(struct phy_device *phydev) | ||
{ | ||
struct device *dev = &phydev->mdio.dev; | ||
struct rtl821x_priv *priv; | ||
u32 phy_id = phydev->drv->phy_id; | ||
@@ -440,10 +449,12 @@ static int rtl8211f_config_init(struct phy_device *phydev) | ||
dev_dbg(dev, | ||
"2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", | ||
val_rxdly ? "enabled" : "disabled"); | ||
} | ||
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+ rtl821x_led_of_init(phydev); | ||
+ | ||
if (priv->has_phycr2) { | ||
ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2, | ||
RTL8211F_CLKOUT_EN, priv->phycr2); | ||
if (ret < 0) { | ||
dev_err(dev, "clkout configuration failed: %pe\n", | ||
-- | ||
Created with Armbian build tools https://github.com/armbian/build |