Add suport for asl and rol to match existing support for asr and ror (a…

…ws#2185)

### Description of changes: 
Looking at aws#2177 I noticed there were
some obvious omissions for the ARM constant tweak. This change adds the
left version of the right instructions we already have in case a
compiler ever decides to use it in the future.

### Testing:
Added new test code for the instructions, also updated delocate_test.go
to print the first difference after printing the total file:
```
--- FAIL: TestDelocate (0.01s)
    --- FAIL: TestDelocate/aarch64-Basic (0.00s)
        delocate_test.go:94: delocated output differed.
            Wanted:
            .text
            .file 1 "inserted_by_delocate.c"
....
            Got:
            .text
            .file 1 "inserted_by_delocate.c"
.....
        delocate_test.go:100:
            First difference at line 187:
            Expected:   "    add x22, sp, #(13*32)+96*32"
            Got:        "\tadd x22, sp, #(13*32)+96*32"
```

By submitting this pull request, I confirm that my contribution is made
under the terms of the Apache 2.0 license and the ISC license.

util/fipstools/delocate/delocate.peg

@@ -87,7 +87,7 @@ RegisterOrConstant <- (('%'[[A-Z]][[A-Z0-9]]*) /
                        ('#(' [0-9]+ ')') /
                        ARMRegister)
                       ![fb:(+\-]
-ARMConstantTweak <- ((([us] "xt" [xwhb]) / "lsl" / "lsr" / "ror" / "asr" / "msl") (WS '#'? Offset)?)/
+ARMConstantTweak <- ((([us] "xt" [xwhb]) / ("lsl" / "lsr" / "ror" / "rol" / "asr" / "asl" / "msl") ![A-Za-z0-9_]) (WS '#'? Offset)?) /
                     "mul vl"  # multiply offset by the hardware's vector length
 ARMRegister <- "sp" / ([xwdqshb] [0-9] [0-9]? !(ARMRegisterBoundary)) / "xzr" / "wzr" / "NZCV" / ARMVectorRegister / SVE2PredicateRegister /
  ('{' WS? ARMVectorRegister WS? ([,\-] WS? ARMVectorRegister)* WS? '}' ('[' [0-9] [0-9]? ']')? )