First version that produced RTL

canal/circuit.py

@@ -1236,7 +1236,7 @@ def __lift_ports(self):
                     # print("\n")
                     self.add_port(port_name, magma.In(magma.Bits[bit_width]))
                     self.wire(self.ports[port_name], self.core.ports[port_name])
-                    #print(self.combinational_ports)
+                    print(self.combinational_ports)
                     if self.ready_valid and port_name not in self.combinational_ports:
                         if "flush" in port_name:
                             continue 

canal/cyclone.py

@@ -482,8 +482,11 @@ def __add_core(self, core: InterconnectCore,
                    CoreConnectionType.Default):
         if connection_type & CoreConnectionType.CB == CoreConnectionType.CB:
             inputs = core.inputs()[:]
+            #print(inputs)
             inputs.sort(key=lambda x: x[1])
             for width, port_name in inputs:
+                #if "mu2io_16_1" in port_name:
+                #    breakpoint()
                 if width == self.track_width:
                     self.inputs.add(port_name)
                     # create node
@@ -494,9 +497,13 @@ def __add_core(self, core: InterconnectCore,
                     self.__port_core[port_name].append(core)
 
         if connection_type & CoreConnectionType.SB == CoreConnectionType.SB:
+
             outputs = core.outputs()[:]
+            print(outputs)
             outputs.sort(key=lambda x: x[1])
             for width, port_name in outputs:
+                #if "io2f_17_0" in port_name:
+                #    breakpoint()
                 if width == self.track_width:
                     self.outputs.add(port_name)
                     # create node

canal/interconnect.py

@@ -266,6 +266,9 @@ def __lift_ports(self):
                             self.wire(p, tile.ports[sb_name + "_ready"])
                             self.__interface[ready_name] = sb_port
 
+    # def connect_matrix_unit_stall_port(self):
+    #     breakpoint()
+
     def __connect_margin_tiles(self):
         # connect these margin tiles
         # margin tiles have empty switchbox

canal/util.py

@@ -193,6 +193,7 @@ def create_uniform_interconnect(width: int,
 
     # insert io
     connect_io(interconnect, io_conn["in"], io_conn["out"], io_sides)
+    #breakpoint()
 
     # insert pipeline register
     if pipeline_reg is None:
@@ -224,10 +225,12 @@ def connect_io(interconnect: InterconnectGraph,
             if x in range(x_min, x_max + 1) and \
                     y in range(y_min, y_max + 1):
                 continue
-
-
+
+            print(f"x, y: {x}, {y}")
+
             # make sure that these margins tiles have empty switch boxes
             tile = interconnect[(x, y)]
+
             # print(f"X: {x}, Y: {y}")
             print(tile.ports)
             if tile.core.core is None:
@@ -248,6 +251,7 @@ def connect_io(interconnect: InterconnectGraph,
                 next_tile = interconnect[(x, y - 1)]
                 side = SwitchBoxSide.SOUTH
             for input_port, conn in input_port_conn.items():
+                #breakpoint()
                 # input is from fabric to IO
                 if input_port in tile.ports:
                     port_node = tile.ports[input_port]
@@ -259,6 +263,11 @@ def connect_io(interconnect: InterconnectGraph,
                             sb_node = next_tile.get_sb(side, track,
                                                        SwitchBoxIO.SB_OUT)
                             sb_node.add_edge(port_node)
+
+            # if "io2f_17_0" in output_port_conn:
+            #     print("Hit breakpoint")
+            #     breakpoint()
+
             for output_port, conn in output_port_conn.items():
                 # output is IO to fabric
                 if output_port in tile.ports: