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Routine commit
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mcoduoza committed Oct 25, 2024
1 parent 96790ba commit 4c96b6d
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Showing 3 changed files with 47 additions and 1 deletion.
11 changes: 11 additions & 0 deletions canal/circuit.py
Original file line number Diff line number Diff line change
Expand Up @@ -1208,6 +1208,7 @@ def __lift_ports(self):
if sb.switchbox.num_track > 0:
continue
# lift the input ports up
#print(self.core)
for bt, port_name in self.core_interface.inputs():
if bt != bit_width:
continue
Expand All @@ -1216,6 +1217,9 @@ def __lift_ports(self):
# if it has no connection, then we lift it up
port_node = self.tiles[bit_width].ports[port_name]
if port_node.get_conn_in():
# print("\nConn in is true!")
# print(port_node)
# print("\n")
cb_input_port = self.cbs[port_name].ports.I
# use the CB input type instead
self.add_port(port_name, cb_input_port.base_type())
Expand All @@ -1227,9 +1231,16 @@ def __lift_ports(self):
p = self.add_port(port_name + "_valid", magma.BitIn)
self.safe_wire(p, self.cbs[port_name].ports.valid_in)
else:
# print("\nConn in is false!")
# print(port_node)
# print("\n")
self.add_port(port_name, magma.In(magma.Bits[bit_width]))
self.wire(self.ports[port_name], self.core.ports[port_name])
#print(self.combinational_ports)
if self.ready_valid and port_name not in self.combinational_ports:
if "flush" in port_name:
continue
# print(f"port name not in combo ports: {port_name}")
core_ready = self.core.ports[port_name + "_ready"]
core_valid = self.core.ports[port_name + "_valid"]
if core_valid.base_type() is magma.In(magma.Bits[1]):
Expand Down
2 changes: 2 additions & 0 deletions canal/interconnect.py
Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,8 @@ def __init__(self, interconnects: Dict[int, InterconnectGraph],
double_buffer=self.double_buffer,
ready_valid=self.ready_valid)

#breakpoint()

# we need to deal with inter-tile connections now
# we only limit mesh

Expand Down
35 changes: 34 additions & 1 deletion canal/util.py
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,10 @@ def compute_num_tracks(x_offset: int, y_offset: int,


def get_array_size(width, height, io_sides):
x_min = 1 if io_sides & IOSide.West else 0
#x_min = 1 if io_sides & IOSide.West else 0

# MO: Temporary hack
x_min = 1
x_max = width - 2 if io_sides & IOSide.East else width - 1
y_min = 1 if io_sides & IOSide.North else 0
y_max = height - 2 if io_sides & IOSide.South else height - 1
Expand Down Expand Up @@ -115,6 +118,7 @@ def create_uniform_interconnect(width: int,

interconnect.add_tile(tile_circuit)
core = column_core_fn(x, y)

core_interface = CoreInterface(core)
interconnect.set_core(x, y, core_interface)

Expand All @@ -132,12 +136,37 @@ def create_uniform_interconnect(width: int,
if tile is not None:
continue
core = column_core_fn(x, y)

#breakpoint()

# Here the MU ports are still alive
# if x == 0 and y == 7:
# print(core.ports)

# They seem to disappear afterwards...figure out where they disappear and why
# Figure out how to alter the io_cons to include mu2f and vice versa

sb = SwitchBox(x, y, 0, track_width, [])
tile_circuit = Tile(x, y, track_width, sb, tile_height)
interconnect.add_tile(tile_circuit)

core_interface = CoreInterface(core)
# if x == 0 and y == 7:
# print(core_interface.inputs())
# print(core_interface.outputs())
#breakpoint()
interconnect.set_core(x, y, core_interface)
# if x == 0 and y == 7:
# print(interconnect[(x, y)].inputs)
# print(interconnect[(x, y)].outputs)
#breakpoint()


#print(interconnect[(0, 7)].ports)
# print(interconnect[(1, 0)].inputs)
# print(interconnect[(1, 0)].outputs)
# print(interconnect[(1, 0)].core)
#breakpoint()
# set port connections
port_names = list(port_connections.keys())
port_names.sort()
Expand Down Expand Up @@ -195,8 +224,12 @@ def connect_io(interconnect: InterconnectGraph,
if x in range(x_min, x_max + 1) and \
y in range(y_min, y_max + 1):
continue


# make sure that these margins tiles have empty switch boxes
tile = interconnect[(x, y)]
# print(f"X: {x}, Y: {y}")
print(tile.ports)
if tile.core.core is None:
continue
assert tile.switchbox.num_track == 0
Expand Down

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