OR incoming readys for MU2F I/O tile: assume only one is used

StanfordAHA · Nov 7, 2024 · cacd637 · cacd637
1 parent d2235ff
commit cacd637
Showing 1 changed file with 4 additions and 1 deletion.
diff --git a/canal/circuit.py b/canal/circuit.py
@@ -1270,7 +1270,10 @@ def __lift_ports(self):
                     if core_ready.base_type() is magma.In(magma.Bits[1]):
                         core_ready = core_ready[0]
                     if len(port_node) > 1:
-                        fanout = FromMagma(mantle.DefineAnd(len(port_node)))
+                        if self.core.name() == "MU2F_IOCoreReadyValid":
+                            fanout = FromMagma(mantle.DefineOr(len(port_node)))
+                        else: 
+                            fanout = FromMagma(mantle.DefineAnd(len(port_node)))
                         fanout.instance_name = port_name + "_ready_merge"
                         p = self.add_port(port_name + "_ready", magma.In(magma.Bits[len(port_node)]))
                         self.wire(fanout.ports.O[0], core_ready)