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fix(MainPipe): fix s1_way_en generate logic when ecc inject occur #4285

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merged 2 commits into from
Feb 20, 2025

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cz4e
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@cz4e cz4e commented Feb 18, 2025

  • When inject tag ecc error io.pseudo_error.valid == 1 and mainpipe request valid (for example io.miss_req.valid == 1
  val s1_need_replacement = s1_req.miss && !s1_tag_match
  val s1_need_eviction = s1_req.miss && !s1_tag_match && s1_repl_coh.state =/= ClientStates.Nothing
  val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way)

when generate s1_way_en, s1_tag_match == 0 cause inject tag ecc error, so s1_need_replacement == 1, but may be target cacheline already in dcache (for example prefetch.w miss), finally there is 2 same paddr cacheline in dcache, obviously this is illegal.

  • Determine whether it is a pseudo error. If it's pseudo error, use no-toggled-tag (which no toggled by cacheCtrl) for generate s1_way_en, otherwise use toggled-tag

@cz4e cz4e added the bug report Bugs to be confirmed label Feb 18, 2025
@cz4e cz4e requested a review from Anzooooo February 18, 2025 07:29
@cz4e cz4e changed the title fix(MainPipe): fix way_en generate logic when ecc inject occur fix(MainPipe): fix s1_way_en generate logic when ecc inject occur Feb 18, 2025
@cz4e cz4e added bug Confirmed bugs and removed bug report Bugs to be confirmed labels Feb 18, 2025
@XiangShanRobot
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[Generated by IPC robot]
commit: 1935160

commit astar copy_and_run coremark gcc gromacs hmmer-Vector lbm linux mcf microbench milc namd povray wrf xalancbmk
1935160 1.819 0.442 2.634 1.228 2.144 1.498 2.145 2.360 0.943 1.380 1.998 3.101 2.547 2.272 3.300

master branch:

commit astar copy_and_run coremark gcc gromacs hmmer-Vector lbm linux mcf microbench milc namd povray wrf xalancbmk
ccd7d22 1.819 1.239 2.144 1.498 2.145 0.943 1.998 3.101 2.272 3.300
fa84f22 1.819 0.442 2.634 1.228 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
3c808de 1.819 0.442 2.634 1.226 2.144 1.498 2.145 2.360 0.943 1.380 1.998 3.101 2.547 2.272 3.300
4ec91ff 1.819 0.442 2.634 1.235 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
2fa6e78 1.819 0.442 2.634 1.232 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
d74a789 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
638f3d8 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
6d8be4c 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.360 0.943 1.380 1.998 3.101 2.547 2.272 3.300
57504f4 1.819 0.442 2.634 1.229 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
ccde527 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300

@XiangShanRobot
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[Generated by IPC robot]
commit: 5eb0b9e

commit astar copy_and_run coremark gcc gromacs hmmer-Vector lbm linux mcf microbench milc namd povray wrf xalancbmk
5eb0b9e 1.819 0.442 2.634 1.233 2.144 1.498 2.145 2.360 0.943 1.380 1.998 3.101 2.547 2.272 3.300

master branch:

commit astar copy_and_run coremark gcc gromacs hmmer-Vector lbm linux mcf microbench milc namd povray wrf xalancbmk
075d493 1.819 0.442 2.634 1.232 2.144 1.498 2.145 2.364 0.943 1.380 1.998 3.101 2.547 2.272 3.300
2df9c39 1.819 1.228 2.144 1.498 2.145 0.943 1.998 3.101 2.272 3.300
ccd7d22 1.819 0.442 2.634 1.239 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
fa84f22 1.819 0.442 2.634 1.228 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
3c808de 1.819 0.442 2.634 1.226 2.144 1.498 2.145 2.360 0.943 1.380 1.998 3.101 2.547 2.272 3.300
4ec91ff 1.819 0.442 2.634 1.235 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
2fa6e78 1.819 0.442 2.634 1.232 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
d74a789 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
638f3d8 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.360 0.943 1.388 1.998 3.101 2.547 2.272 3.300
6d8be4c 1.819 0.442 2.634 1.231 2.144 1.498 2.145 2.360 0.943 1.380 1.998 3.101 2.547 2.272 3.300

@linjuanZ linjuanZ merged commit 302eb94 into master Feb 20, 2025
10 checks passed
@linjuanZ linjuanZ deleted the fix-mainpipe-way-en branch February 20, 2025 02:38
ChrisYzcc pushed a commit to ChrisYzcc/XiangShan that referenced this pull request Feb 22, 2025
…penXiangShan#4285)

* When inject tag ecc error `io.pseudo_error.valid == 1` and mainpipe
request valid (for example `io.miss_req.valid == 1`
```
  val s1_need_replacement = s1_req.miss && !s1_tag_match
  val s1_need_eviction = s1_req.miss && !s1_tag_match && s1_repl_coh.state =/= ClientStates.Nothing
  val s1_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_tag_match_way)
```
when generate `s1_way_en`, `s1_tag_match == 0` cause inject tag ecc
error, so `s1_need_replacement == 1`, but may be target cacheline
already in dcache (for example `prefetch.w` miss), finally there is 2
same paddr cacheline in dcache, obviously this is illegal.

* Determine whether it is a pseudo error. If it's pseudo error, use
no-toggled-tag (which no toggled by cacheCtrl) for generate `s1_way_en`,
otherwise use toggled-tag
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3 participants