feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
  * fflags, fcsr,
  * vxsat, vcsr, vstart,
  * mstatus, sstatus, hstatus, vsstatus, mnstatus,
  * dcsr.
* The reason for Inorder CSRR executed is that these CSR will be changed
  by Use-Level instruction without any fence, and executing OoO would
  get wrong result.
* Since there must be FENCE before reading any PMC CSRs, there is no
  need to let reading PMC CSRs inorder.

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -34,6 +34,7 @@ import xiangshan.backend.fu.NewCSR.CSRNamedConstant.ContextStatus
 import xiangshan.backend.rob.RobPtr
 import utils.MathUtils.{BigIntGenMask, BigIntNot}
 import xiangshan.backend.trace._
+import freechips.rocketchip.rocket.CSRs
 
 class FpuCsrIO extends Bundle {
   val fflags = Output(Valid(UInt(5.W)))
@@ -1639,7 +1640,7 @@ class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
   }
 }
 */
-class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst  {
+class PFEvent(implicit p: Parameters) extends XSModule {
   val io = IO(new Bundle {
     val distribute_csr = Flipped(new DistributedCSRIO())
     val hpmevent = Output(Vec(29, UInt(XLEN.W)))
@@ -1653,7 +1654,7 @@ class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst  {
                    List.fill(5)(RegInit("hc0300c0300".U(XLEN.W)))
 
   val perfEventMapping = (0 until 29).map(i => {Map(
-    MaskedRegMap(addr = Mhpmevent3 +i,
+    MaskedRegMap(addr = CSRs.mhpmevent3 + i,
                  reg  = perfEvents(i),
                  wmask = "hf87fff3fcff3fcff".U(XLEN.W))
   )}).fold(Map())((a,b) => a ++ b)

src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala

@@ -0,0 +1,23 @@
+package xiangshan.backend.fu.NewCSR
+
+import freechips.rocketchip.rocket.CSRs
+
+object CSROoORead {
+  /**
+   * "Read only" CSRs that can be fully pipelined when read in CSRR instruction.
+   * Only read by csr instructions.
+   */
+  val inOrderCsrReadList = List(
+    CSRs.fflags,
+    CSRs.fcsr,
+    CSRs.vxsat,
+    CSRs.vcsr,
+    CSRs.vstart,
+    CSRs.sstatus,
+    CSRs.vsstatus,
+    CSRs.mstatus,
+    CSRs.hstatus,
+    CSRs.mnstatus,
+    CSRs.dcsr,
+  )
+}

src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala

@@ -5,7 +5,6 @@ import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import xiangshan.cache.HasDCacheParameters
 import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState
-import xiangshan.backend.fu.util.CSRConst
 import xiangshan.backend.fu.util.SdtrigExt
 import xiangshan._
 import utils._

src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala

@@ -7,7 +7,6 @@ import utils._
 import xiangshan.ExceptionNO
 import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, PrivState, XtvecBundle}
 import xiangshan.backend.fu.NewCSR.CSRDefines.{PrivMode, XtvecMode}
-import xiangshan.backend.fu.util.CSRConst
 import xiangshan.backend.fu.NewCSR.InterruptNO
 
 

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -13,7 +13,6 @@ import xiangshan.backend.fu.NewCSR.CSRDefines._
 import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
 import xiangshan.backend.fu.NewCSR.CSREvents.{CSREvents, DretEventSinkBundle, EventUpdatePrivStateOutput, MNretEventSinkBundle, MretEventSinkBundle, SretEventSinkBundle, TargetPCBundle, TrapEntryDEventSinkBundle, TrapEntryEventInput, TrapEntryHSEventSinkBundle, TrapEntryMEventSinkBundle, TrapEntryMNEventSinkBundle, TrapEntryVSEventSinkBundle}
 import xiangshan.backend.fu.fpu.Bundles.Frm
-import xiangshan.backend.fu.util.CSRConst
 import xiangshan.backend.fu.vector.Bundles.{Vl, Vstart, Vxrm, Vxsat}
 import xiangshan.backend.fu.wrapper.CSRToDecode
 import xiangshan.backend.rob.RobPtr
@@ -938,6 +937,15 @@ class NewCSR(implicit val p: Parameters) extends Module
     triggerFrontendChange || floatStatusOnOff || vectorStatusOnOff ||
     vstartChange || frmChange
 
+  /**
+   * Look up id in vsMapS and sMapVS.
+   * If id is in vsMapS, use vsMapS(id) when under VS mode,
+   *                         id under other modes
+   * Else If id is in sMapVS, use 0 when under VS mode,
+   *                              id under modes except VS
+   * Else, use id as read address
+   * Use read address to look up rdata in csrRwMap
+   */
   private val rdata = Mux1H(csrRwMap.map { case (id, (_, rdata)) =>
     if (vsMapS.contains(id)) {
       ((isModeVS && addr === vsMapS(id).U) || !isModeVS && addr === id.U) -> rdata

src/main/scala/xiangshan/backend/fu/PMP.scala

@@ -28,6 +28,7 @@ import xiangshan.backend.fu.util.HasCSRConst
 import utils._
 import utility._
 import xiangshan.cache.mmu.{TlbCmd, TlbExceptionBundle}
+import freechips.rocketchip.rocket.CSRs
 
 trait PMPConst extends HasPMParameters {
   val PMPOffBits = 2 // minimal 4bytes
@@ -354,7 +355,7 @@ class PMP(implicit p: Parameters) extends PMPXSModule with HasXSParameter with P
   val pmp = Wire(Vec(NumPMP, new PMPEntry()))
   val pma = Wire(Vec(NumPMA, new PMPEntry()))
 
-  val pmpMapping = pmp_gen_mapping(pmp_init, NumPMP, PmpcfgBase, PmpaddrBase, pmp)
+  val pmpMapping = pmp_gen_mapping(pmp_init, NumPMP, CSRs.pmpcfg0, CSRs.pmpaddr0, pmp)
   val pmaMapping = pmp_gen_mapping(pma_init, NumPMA, PmacfgBase, PmaaddrBase, pma)
   val mapping = pmpMapping ++ pmaMapping