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Increase coverage and some minor fixes. #467

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Oct 11, 2022
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8222498
test no graph safety code
Christian-B Aug 16, 2022
5599775
test view Placements better
Christian-B Aug 16, 2022
defce1a
test only 1 graph
Christian-B Aug 16, 2022
56272f0
flake8
Christian-B Aug 17, 2022
e0fe33f
include soft reset
Christian-B Aug 17, 2022
4012e30
test SplitterOneAppOneMachine
Christian-B Aug 17, 2022
0f65df7
newline at end of file
Christian-B Aug 19, 2022
effce8d
test splitter_fixed_legacy
Christian-B Aug 19, 2022
d9ddac1
TestSplitterFixedLegacy
Christian-B Aug 20, 2022
6170d38
verify api before using api
Christian-B Aug 21, 2022
4282a17
comment out test currently broken
Christian-B Aug 21, 2022
b48c4e7
flake8
Christian-B Aug 21, 2022
de37353
more tests
Christian-B Aug 23, 2022
a30cf85
test fixes
Christian-B Aug 23, 2022
4faaac9
fix test
Christian-B Aug 23, 2022
25f93e0
test splitter_reset
Christian-B Aug 23, 2022
5c85d57
more tests
Christian-B Aug 23, 2022
f70eb6d
get_edges_starting_at_vertex removed as unused
Christian-B Aug 23, 2022
c69d84e
more tests
Christian-B Aug 23, 2022
f383c41
test EdgePartition
Christian-B Aug 23, 2022
2f3d39e
flake8
Christian-B Aug 25, 2022
6499ffd
test ConstantSDRAMMachinePartition
Christian-B Aug 25, 2022
3f5055c
flake8
Christian-B Aug 25, 2022
2ca3803
test AbstractOneAppOneMachineVertex
Christian-B Aug 30, 2022
8e726ff
test edge.label
Christian-B Aug 30, 2022
24f2b96
simplify and test Vertex.add_constraint bad value
Christian-B Aug 30, 2022
f4faa0a
test slice gets int values
Christian-B Aug 30, 2022
e9212b0
more testing
Christian-B Aug 30, 2022
98062d8
revert to master
Christian-B Aug 30, 2022
b6ffc4f
dont return None when an Exception is better
Christian-B Aug 30, 2022
c611784
test sdram partitions
Christian-B Aug 30, 2022
356dd8d
flake8
Christian-B Aug 30, 2022
a2abeba
checks before sets
Christian-B Aug 30, 2022
1351912
flake8
Christian-B Aug 30, 2022
736d3d9
more model tests
Christian-B Aug 30, 2022
8a3b0e6
more splitter coverage
Christian-B Aug 30, 2022
55a4521
flake8
Christian-B Aug 30, 2022
cfe27bd
flake8
Christian-B Aug 30, 2022
653b683
pylint
Christian-B Aug 31, 2022
7fec590
placements coverage
Christian-B Aug 31, 2022
a8e1761
sdram testing
Christian-B Aug 31, 2022
083e018
remove blank lines
Christian-B Aug 31, 2022
7af37ec
fix and test equals
Christian-B Aug 31, 2022
95bac8d
test merged_routing_table_generator
Christian-B Aug 31, 2022
bf2a583
flake8
Christian-B Aug 31, 2022
f34a0c3
more testing
Christian-B Aug 31, 2022
669eb13
Use peek and pop methods rather than properties
Christian-B Sep 1, 2022
c79233f
Use peek and pop methods rather than properties
Christian-B Sep 1, 2022
f16b7dd
remove usless code
Christian-B Sep 1, 2022
0782217
more table generator tests
Christian-B Sep 1, 2022
b22b5d5
add ChipAndCoreConstraint to tests
Christian-B Sep 1, 2022
096e64a
test setting tags
Christian-B Sep 1, 2022
5a8d018
merge
Christian-B Sep 12, 2022
2d43bb9
remove tests for changed code
Christian-B Sep 12, 2022
7667fa0
merged in master
Christian-B Sep 14, 2022
8aaf237
if on generator is always True
Christian-B Sep 15, 2022
d86183e
if no incomming connections return empty list
Christian-B Sep 15, 2022
15404f1
flake8
Christian-B Sep 15, 2022
56e02db
remove blank line
Christian-B Sep 15, 2022
586ea44
merged in master
Christian-B Sep 15, 2022
28aa448
retes with reverse
Christian-B Sep 15, 2022
7bb1105
remove uneeded f string
Christian-B Sep 15, 2022
ace6e49
testing and type doc fixing
Christian-B Sep 15, 2022
c79f21c
test_routing_tree.py
Christian-B Sep 16, 2022
907c8a6
remove debug value
Christian-B Sep 16, 2022
948660b
merge
Christian-B Sep 16, 2022
7e49816
fix test after merge
Christian-B Sep 16, 2022
dd20b78
merge
Christian-B Sep 21, 2022
6730bcb
merged in master
Christian-B Sep 26, 2022
2742331
merged in master
Christian-B Sep 26, 2022
c9495aa
merge
Christian-B Sep 27, 2022
343433a
merge fixes
Christian-B Sep 27, 2022
b40e707
flake8
Christian-B Sep 27, 2022
6cdd9f9
merged in master
Christian-B Sep 28, 2022
0398d10
merged in master
Christian-B Sep 30, 2022
925e5ef
fix test after merge
Christian-B Oct 3, 2022
32fa595
Merge branch 'master' into coverage
Christian-B Oct 11, 2022
da5574e
put back parameter doc
Christian-B Oct 11, 2022
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2 changes: 1 addition & 1 deletion pacman/model/graphs/abstract_single_source_partition.py
Original file line number Diff line number Diff line change
Expand Up @@ -35,10 +35,10 @@ def __init__(

@overrides(AbstractEdgePartition.add_edge)
def add_edge(self, edge):
super().add_edge(edge)
if edge.pre_vertex != self._pre_vertex:
raise PacmanConfigurationException(
"A partition can only contain edges with the same pre_vertex")
super().add_edge(edge)

@property
def pre_vertex(self):
Expand Down
5 changes: 3 additions & 2 deletions pacman/model/graphs/application/application_fpga_vertex.py
Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,9 @@ def incoming_fpga_connections(self):

:rtype: iter(FPGAConnection)
"""
for conn in self._incoming_fpga_connections:
yield from conn.expanded
if self._incoming_fpga_connections:
for conn in self._incoming_fpga_connections:
yield from conn.expanded

@property
def outgoing_fpga_connection(self):
Expand Down
39 changes: 3 additions & 36 deletions pacman/model/graphs/application/application_graph.py
Original file line number Diff line number Diff line change
Expand Up @@ -102,15 +102,15 @@ def add_edge(self, edge, outgoing_edge_partition_name):
added to this partition that start at a different vertex to this
one
"""
self._check_edge(edge)
# Add the edge to the partition
partition = self.get_outgoing_edge_partition_starting_at_vertex(
edge.pre_vertex, outgoing_edge_partition_name)
if partition is None:
partition = ApplicationEdgePartition(
identifier=outgoing_edge_partition_name,
pre_vertex=edge.pre_vertex)
self.add_outgoing_edge_partition(partition)
self._check_edge(edge)
self._add_outgoing_edge_partition(partition)
partition.add_edge(edge)
return partition

Expand Down Expand Up @@ -151,50 +151,17 @@ def edges(self):
for partition in self.outgoing_edge_partitions
for edge in partition.edges]

def add_outgoing_edge_partition(self, edge_partition):
def _add_outgoing_edge_partition(self, edge_partition):
""" Add an edge partition to the graph.

Will also add any edges already in the partition as well

:param ApplicationEdgePartition edge_partition:
The edge partition to add
:raises PacmanAlreadyExistsException:
If a partition already exists with the same pre_vertex and
identifier
"""
# verify that this partition is suitable for this graph
if not isinstance(edge_partition, ApplicationEdgePartition):
raise PacmanInvalidParameterException(
"outgoing_edge_partition", edge_partition.__class__,
"Partitions must be an ApplicationEdgePartition")

# check this partition doesn't already exist
key = (edge_partition.pre_vertex,
edge_partition.identifier)
if edge_partition in self._outgoing_edge_partitions_by_pre_vertex[
edge_partition.pre_vertex]:
raise PacmanAlreadyExistsException(
str(ApplicationEdgePartition), key)

self._outgoing_edge_partitions_by_pre_vertex[
edge_partition.pre_vertex].add(edge_partition)
for edge in edge_partition.edges:
self._check_edge(edge)

self._n_outgoing_edge_partitions += 1

def get_edges_starting_at_vertex(self, vertex):
""" Get all the edges that start at the given vertex.

:param AbstractVertex vertex:
The vertex at which the edges to get start
:rtype: iterable(AbstractEdge)
"""
parts = self.get_outgoing_edge_partitions_starting_at_vertex(vertex)
for partition in parts:
for edge in partition.edges:
yield edge

@property
def outgoing_edge_partitions(self):
""" The edge partitions in the graph.
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,7 @@ def get_sdram_base_address_for(self, vertex):

@overrides(AbstractSDRAMPartition.get_sdram_size_of_region_for)
def get_sdram_size_of_region_for(self, vertex):
if len(self._edges) == 0:
return 0
return self._edges.peek().sdram_size
if self._sdram_size is None:
raise PartitionMissingEdgesException(
self.MISSING_EDGE_ERROR_MESSAGE.format(self))
return self._sdram_size
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,8 @@

from spinn_utilities.overrides import overrides
from pacman.exceptions import (
PacmanConfigurationException, PartitionMissingEdgesException)
PacmanConfigurationException, PartitionMissingEdgesException,
PacmanValueError)
from pacman.model.graphs import AbstractSingleSourcePartition
from pacman.model.graphs.machine import (
AbstractSDRAMPartition, SDRAMMachineEdge)
Expand Down Expand Up @@ -77,7 +78,7 @@ def get_sdram_base_address_for(self, vertex):
for edge in self._edges:
if edge.post_vertex == vertex:
return edge.sdram_base_address
return None
raise PacmanValueError(f"Vertex {vertex} is not in this partition")

@overrides(AbstractSDRAMPartition.get_sdram_size_of_region_for)
def get_sdram_size_of_region_for(self, vertex):
Expand All @@ -86,4 +87,4 @@ def get_sdram_size_of_region_for(self, vertex):
for edge in self._edges:
if edge.post_vertex == vertex:
return edge.sdram_size
return None
raise PacmanValueError(f"Vertex {vertex} is not in this partition")
Original file line number Diff line number Diff line change
Expand Up @@ -55,52 +55,52 @@ def sdram_base_address(self):

@overrides(AbstractMultiplePartition.add_edge)
def add_edge(self, edge):
# add
super().add_edge(edge)

# check
if len(self._destinations.keys()) != 1:
if len(self._destinations):
if edge.post_vertex not in self._destinations:
raise PacmanConfigurationException(
"The {} can only support 1 destination vertex".format(
self.__class__.__name__))
try:
if len(self._pre_vertices[edge.pre_vertex]) != 0:
raise PacmanConfigurationException(
f"The {self.__class__.__name__} only supports 1 edge from "
f"a given pre vertex.")
except KeyError as ex:
raise PacmanConfigurationException(
"The {} can only support 1 destination vertex".format(
self.__class__.__name__))
if len(self._pre_vertices[edge.pre_vertex]) != 1:
raise PacmanConfigurationException(
"The {} only supports 1 edge from a given pre vertex.".format(
self.__class__.__name__))

if self._sdram_base_address is not None:
raise PacmanConfigurationException(
"Illegal attempt to add an edge after sdram_base_address set")
"Edge pre_vertex is not a Partition. pre vertex") from ex
# add
super().add_edge(edge)

@sdram_base_address.setter
def sdram_base_address(self, new_value):
if len(self.pre_vertices) != len(self.edges):
raise PartitionMissingEdgesException(
f"There are {len(self.pre_vertices)} pre vertices "
f"but only {len(self.edges)} edges")

self._sdram_base_address = new_value

for pre_vertex in self._pre_vertices.keys():
try:
# allocate for the pre_vertex
edge = self._pre_vertices[pre_vertex].peek()
edge.sdram_base_address = new_value
new_value += edge.sdram_size
except KeyError as e:
raise PartitionMissingEdgesException(
"This partition has no edge from {}".format(
pre_vertex)) from e
# allocate for the pre_vertex
edge = self._pre_vertices[pre_vertex].peek()
edge.sdram_base_address = new_value
new_value += edge.sdram_size

@overrides(AbstractSDRAMPartition.get_sdram_base_address_for)
def get_sdram_base_address_for(self, vertex):
if self._sdram_base_address is None:
return None
if vertex in self._pre_vertices:
for edge in self._edges:
if edge.pre_vertex == vertex:
return edge.sdram_base_address
edge = self._pre_vertices[vertex].peek()
return edge.sdram_base_address
else:
return self._sdram_base_address

@overrides(AbstractSDRAMPartition.get_sdram_size_of_region_for)
def get_sdram_size_of_region_for(self, vertex):
if vertex in self._pre_vertices:
for edge in self._edges:
if edge.pre_vertex == vertex:
return edge.sdram_size
edge = self._pre_vertices[vertex].peek()
return edge.sdram_size
else:
return self.total_sdram_requirements()
33 changes: 16 additions & 17 deletions pacman/model/partitioner_splitters/splitter_external_device.py
Original file line number Diff line number Diff line change
Expand Up @@ -48,23 +48,22 @@ def set_governed_app_vertex(self, app_vertex):

if isinstance(app_vertex, ApplicationFPGAVertex):
# This can have multiple FPGA connections per board
if app_vertex.incoming_fpga_connections:
for fpga in app_vertex.incoming_fpga_connections:
for i in range(app_vertex.n_machine_vertices_per_link):
label = (
f"Incoming Machine vertex {i} for"
f" {app_vertex.label}"
f":{fpga.fpga_id}:{fpga.fpga_link_id}"
f":{fpga.board_address}:{fpga.chip_coords}")
vertex_slice = app_vertex.get_incoming_slice_for_link(
fpga, i)
vertex = MachineFPGAVertex(
fpga.fpga_id, fpga.fpga_link_id,
fpga.board_address, fpga.chip_coords, label=label,
app_vertex=app_vertex, vertex_slice=vertex_slice,
incoming=True, outgoing=False)
self.__incoming_vertices.append(vertex)
self.__incoming_slices.append(vertex_slice)
for fpga in app_vertex.incoming_fpga_connections:
for i in range(app_vertex.n_machine_vertices_per_link):
label = (
f"Incoming Machine vertex {i} for"
f" {app_vertex.label}"
f":{fpga.fpga_id}:{fpga.fpga_link_id}"
f":{fpga.board_address}:{fpga.chip_coords}")
vertex_slice = app_vertex.get_incoming_slice_for_link(
fpga, i)
vertex = MachineFPGAVertex(
fpga.fpga_id, fpga.fpga_link_id,
fpga.board_address, fpga.chip_coords, label=label,
app_vertex=app_vertex, vertex_slice=vertex_slice,
incoming=True, outgoing=False)
self.__incoming_vertices.append(vertex)
self.__incoming_slices.append(vertex_slice)
fpga = app_vertex.outgoing_fpga_connection
if fpga is not None:
label = (
Expand Down
7 changes: 6 additions & 1 deletion pacman/model/resources/multi_region_sdram.py
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,12 @@ def nest(self, region, other):
self._per_timestep_sdram + other.per_timestep
if region in self.__regions:
if isinstance(other, MultiRegionSDRAM):
self.__regions[region].merge(other)
if isinstance(self.__regions[region], MultiRegionSDRAM):
self.__regions[region].merge(other)
else:
old = self.__regions[region]
other.add_cost(region, old.fixed, old.per_timestep)
self.__regions[region] = other
else:
self.__regions[region] += other
else:
Expand Down
2 changes: 2 additions & 0 deletions pacman/model/resources/reverse_iptag_resource.py
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,8 @@ def __repr__(self):
)

def __eq__(self, other):
if not isinstance(other, ReverseIPtagResource):
return False
return (self._port == other._port and
self._sdp_port == other._sdp_port and
self._tag == other._tag)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -55,14 +55,14 @@ def __create_routing_table(x, y, partitions_in_table, routing_info):
table = UnCompressedMulticastRoutingTable(x, y)
iterator = _IteratorWithNext(partitions_in_table.items())
while iterator.has_next:
(vertex, part_id), entry = iterator.next
(vertex, part_id), entry = iterator.pop()
r_info = routing_info.get_routing_info_from_pre_vertex(vertex, part_id)
if r_info is None:
raise Exception(
f"Missing Routing information for {vertex}, {part_id}")
entries = [(vertex, part_id, entry, r_info)]
while __match(iterator, vertex, part_id, r_info, entry, routing_info):
(vertex, part_id), entry = iterator.next
(vertex, part_id), entry = iterator.pop()
r_info = routing_info.get_routing_info_from_pre_vertex(
vertex, part_id)
entries.append((vertex, part_id, entry, r_info))
Expand All @@ -71,9 +71,6 @@ def __create_routing_table(x, y, partitions_in_table, routing_info):
for entry in __merged_keys_and_masks(entries, routing_info):
table.add_multicast_routing_entry(entry)

for source_vertex, partition_id in partitions_in_table:
entry = partitions_in_table[source_vertex, partition_id]

return table


Expand All @@ -82,7 +79,7 @@ def __match(iterator, vertex, part_id, r_info, entry, routing_info):
return False
if isinstance(vertex, ApplicationVertex):
return False
(next_vertex, next_part_id), next_entry = iterator.peek
(next_vertex, next_part_id), next_entry = iterator.peek()
if isinstance(next_vertex, ApplicationVertex):
return False
if part_id != next_part_id:
Expand Down Expand Up @@ -128,18 +125,6 @@ def __merged_keys_and_masks(entries, routing_info):
yield from app_r_info.merge_machine_entries(entries)


def __create_entry(key_and_mask, entry):
"""
:param BaseKeyAndMask key_and_mask:
:param MulticastRoutingTableByPartitionEntry entry:
:rtype: MulticastRoutingEntry
"""
return MulticastRoutingEntry(
routing_entry_key=key_and_mask.key_combo,
defaultable=entry.defaultable, mask=key_and_mask.mask,
link_ids=entry.link_ids, processor_ids=entry.processor_ids)


class _IteratorWithNext(object):

def __init__(self, iterable):
Expand All @@ -151,16 +136,14 @@ def __init__(self, iterable):
self.__next = None
self.__has_next = False

@property
def peek(self):
return self.__next

@property
def has_next(self):
return self.__has_next

@property
def next(self):
def pop(self):
if not self.__has_next:
raise StopIteration
nxt = self.__next
Expand Down
12 changes: 4 additions & 8 deletions pacman/utilities/algorithm_utilities/routing_tree.py
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ def __init__(self, chip, label=None):
:param tuple(int,int) chip:
The chip the route is currently passing through.
"""
self.chip = chip
self._chip_x, self._chip_y = chip
self._children = []
self._label = label

Expand All @@ -63,10 +63,6 @@ def chip(self):
"""
return (self._chip_x, self._chip_y)

@chip.setter
def chip(self, chip):
self._chip_x, self._chip_y = chip

@property
def children(self):
"""
Expand All @@ -91,22 +87,22 @@ def children(self):
additional logic may be required to determine what core to target to\
reach the vertex.

:rtype: iterable(RoutingTree or MachineVertex)
:rtype: iterable(tuple(int, RoutingTree or MachineVertex))
"""
for child in self._children:
yield child

def append_child(self, child):
"""
:param child:
:type child: RoutingTree or MachineVertex
:type child: tuple(int, RoutingTree or MachineVertex)
"""
self._children.append(child)

def remove_child(self, child):
"""
:param child:
:type child: RoutingTree or MachineVertex
:type child: tuple(int, RoutingTree or MachineVertex)
"""
self._children.remove(child)

Expand Down
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