Stage 2: SPIR-V setup

[Snektron]

This pull request introduces the initial setup for a self-hosted stage 2 SPIR-V backend. It includes the following things:

• I wrote a quick tool that can generate Zig-code from SPIR-V JSON specifications. A description of the schema of such a specification can be found on the Khronos website. Specification JSON files can be obtained from the SPIR-V headers project. The generator supports both core and extension grammars, and simply generates all enums and bit fields. This should help to make the code generation a bit more sane.
• A generated spec for the SPIR-V core grammar was added.
• 2 new architectures are added (spirv32 and spirv64), and 3 new operating systems are defined (OpenCL, GLSL450 and Vulkan).
  • SPIR-V requires a memory model to be specified for the final module. This operation takes an addressing mode (either Logical, Physical32 or Physical64, among others), and a memory model itself.
  • The GLSL450 and Vulkan memory models only support the logical addressing mode. In this mode, pointers are opaque. For these architectures, the difference between spirv32 and spirv64 will simply be the integer used for usize. Note that for Vulkan targets, 64-bit (as well as 8 and 16-bit) integers need to be explicitly enabled.
  • The OpenCL memory models support the Physical32 and Physical64 addressing models as well. spirv32 and spirv64 map to Physical32 and Physical64 respectively.
• Finally, i made a setup for linker and codegen for the SPIR-V binary format. Currently, it is capable of generating a very basic binary containing the SPIR-V header and some initial capability and memory model instructions.

Related: #2683