Be somewhat clearer about upper bits in the codegen.

This is a bit of a hodgepodge of changes, but there are three major things: 1. Get rid of all the "weird" sized ints, none of which we see in practise, and which we thus have low confidence are correct. 2. Simplify some of the zero extension stuff. 3. Zero extend all values to 64 bits before a call. We do this crudely for now.
ykjit · Jan 22, 2025 · 4b3b0ca · 4b3b0ca
1 parent a70179c
commit 4b3b0ca
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Showing 4 changed files with 233 additions and 315 deletions.
diff --git a/ykrt/src/compile/jitc_yk/codegen/x64/lsregalloc.rs b/ykrt/src/compile/jitc_yk/codegen/x64/lsregalloc.rs
@@ -829,15 +829,17 @@ impl LSRegAlloc<'_> {
             RegState::FromInst(iidx) => {
                 if self.spills[usize::from(iidx)] == SpillState::Empty {
                     let inst = self.m.inst(iidx);
-                    let size = inst.def_byte_size(self.m);
-                    self.stack.align(size); // FIXME
-                    let frame_off = self.stack.grow(size);
+                    let bitw = inst.def_bitw(self.m);
+                    let bytew = inst.def_byte_size(self.m);
+                    debug_assert!(bitw >= bytew);
+                    self.stack.align(bytew);
+                    let frame_off = self.stack.grow(bytew);
                     let off = i32::try_from(frame_off).unwrap();
-                    match size {
-                        1 => dynasm!(asm; mov BYTE [rbp - off], Rb(reg.code())),
-                        2 => dynasm!(asm; mov WORD [rbp - off], Rw(reg.code())),
-                        4 => dynasm!(asm; mov DWORD [rbp - off], Rd(reg.code())),
-                        8 => dynasm!(asm; mov QWORD [rbp - off], Rq(reg.code())),
+                    match bitw {
+                        8 => dynasm!(asm; mov BYTE [rbp - off], Rb(reg.code())),
+                        16 => dynasm!(asm; mov WORD [rbp - off], Rw(reg.code())),
+                        32 => dynasm!(asm; mov DWORD [rbp - off], Rd(reg.code())),
+                        64 => dynasm!(asm; mov QWORD [rbp - off], Rq(reg.code())),
                         _ => unreachable!(),
                     }
                     self.spills[usize::from(iidx)] = SpillState::Stack(off);
@@ -1380,13 +1382,15 @@ impl LSRegAlloc<'_> {
             RegState::FromInst(iidx) => {
                 if self.spills[usize::from(iidx)] == SpillState::Empty {
                     let inst = self.m.inst(iidx);
-                    let size = inst.def_byte_size(self.m);
-                    self.stack.align(size); // FIXME
-                    let frame_off = self.stack.grow(size);
+                    let bitw = inst.def_bitw(self.m);
+                    let bytew = inst.def_byte_size(self.m);
+                    debug_assert!(bitw >= bytew);
+                    self.stack.align(bytew);
+                    let frame_off = self.stack.grow(bytew);
                     let off = i32::try_from(frame_off).unwrap();
-                    match size {
-                        4 => dynasm!(asm ; movss [rbp - off], Rx(reg.code())),
-                        8 => dynasm!(asm ; movsd [rbp - off], Rx(reg.code())),
+                    match bitw {
+                        32 => dynasm!(asm ; movss [rbp - off], Rx(reg.code())),
+                        64 => dynasm!(asm ; movsd [rbp - off], Rx(reg.code())),
                         _ => unreachable!(),
                     }
                     self.spills[usize::from(iidx)] = SpillState::Stack(off);