SIMD Floating-point add and sub implementation. (WebAssembly#786)

Including: f32x4.add, f64x2.add, f32x4.sub, f64x2.sub
vmosone · Mar 4, 2018 · 1962691 · 1962691
1 parent c0e3c8a
commit 1962691
Show file tree

Hide file tree

Showing 7 changed files with 8,128 additions and 7,833 deletions.
diff --git a/src/binary-reader.cc b/src/binary-reader.cc
@@ -857,6 +857,10 @@ Result BinaryReader::ReadFunctionBody(Offset end_offset) {
       case Opcode::F64X2Min:
       case Opcode::F32X4Max:
       case Opcode::F64X2Max:
+      case Opcode::F32X4Add:
+      case Opcode::F64X2Add:
+      case Opcode::F32X4Sub:
+      case Opcode::F64X2Sub:
         ERROR_UNLESS_OPCODE_ENABLED(opcode);
         CALLBACK(OnBinaryExpr, opcode);
         CALLBACK0(OnOpcodeBare);

diff --git a/src/interp.cc b/src/interp.cc
@@ -2863,6 +2863,22 @@ Result Thread::Run(int num_instructions) {
       case Opcode::F64X2Max:
         CHECK_TRAP(SimdBinop<v128, int64_t>(FloatMax<double>));
         break;
+
+      case Opcode::F32X4Add:
+        CHECK_TRAP(SimdBinop<v128, int32_t>(Add<float>));
+        break;
+
+      case Opcode::F64X2Add:
+        CHECK_TRAP(SimdBinop<v128, int64_t>(Add<double>));
+        break;
+
+      case Opcode::F32X4Sub:
+        CHECK_TRAP(SimdBinop<v128, int32_t>(Sub<float>));
+        break;
+
+      case Opcode::F64X2Sub:
+        CHECK_TRAP(SimdBinop<v128, int64_t>(Sub<double>));
+        break;
       // The following opcodes are either never generated or should never be
       // executed.
       case Opcode::Block:
@@ -3428,7 +3444,11 @@ void Thread::Trace(Stream* stream) {
     case Opcode::F32X4Min:
     case Opcode::F64X2Min:
     case Opcode::F32X4Max:
-    case Opcode::F64X2Max: {
+    case Opcode::F64X2Max:
+    case Opcode::F32X4Add:
+    case Opcode::F64X2Add:
+    case Opcode::F32X4Sub:
+    case Opcode::F64X2Sub: {
       stream->Writef("%s $0x%08x %08x %08x %08x  $0x%08x %08x %08x %08x\n", opcode.GetName(), Pick(2).v128_bits.v[0],
                        Pick(2).v128_bits.v[1], Pick(2).v128_bits.v[2], Pick(2).v128_bits.v[3],Pick(1).v128_bits.v[0],
                        Pick(1).v128_bits.v[1], Pick(1).v128_bits.v[2], Pick(1).v128_bits.v[3]);
@@ -3832,6 +3852,10 @@ void Environment::Disassemble(Stream* stream,
       case Opcode::F64X2Min:
       case Opcode::F32X4Max:
       case Opcode::F64X2Max:
+      case Opcode::F32X4Add:
+      case Opcode::F64X2Add:
+      case Opcode::F32X4Sub:
+      case Opcode::F64X2Sub:
         stream->Writef("%s %%[-2], %%[-1]\n", opcode.GetName());
         break;
 

diff --git a/src/opcode.cc b/src/opcode.cc
@@ -287,6 +287,10 @@ bool Opcode::IsEnabled(const Features& features) const {
     case Opcode::F64X2Min:
     case Opcode::F32X4Max:
     case Opcode::F64X2Max:
+    case Opcode::F32X4Add:
+    case Opcode::F64X2Add:
+    case Opcode::F32X4Sub:
+    case Opcode::F64X2Sub:
       return features.simd_enabled();
 
     // Interpreter opcodes are never "enabled".

diff --git a/src/opcode.def b/src/opcode.def
@@ -341,6 +341,10 @@ WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x76,  F32X4Min, "f32x4.min")
 WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x77,  F64X2Min, "f64x2.min")
 WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x78,  F32X4Max, "f32x4.max")
 WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x79,  F64X2Max, "f64x2.max")
+WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x7a,  F32X4Add, "f32x4.add")
+WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x7b,  F64X2Add, "f64x2.add")
+WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x7c,  F32X4Sub, "f32x4.sub")
+WABT_OPCODE(V128, V128, V128, ___, 0, 0xfd, 0x7d,  F64X2Sub, "f64x2.sub")
 
 
 WABT_OPCODE(I32, I32, I32, ___, 4, 0xfe,  0x00, AtomicWake, "atomic.wake")