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[KERNEL] int8 quantization kernel refactoring & optimization WIP #5146

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@ZelboK ZelboK commented May 31, 2024

This refactors the int8 quantization kernel so that it will optimize f32 -> i8. However, please note that fp16 will require use of half2 though. That can be done with some template specializations but for brevity I will leave that outside of this PR for now.

  1. Reorders instructions to improve ILP with unrolling(manual unrolling can also be done)
  2. Use vectorized loads and stores for fp32, this will significantly increase memory throughput.
  3. Refactors to use the reciprocal of the scale so that we can avoid doing division on the GPU, which is categorically slower because of how many more instructions it leads to.
  4. From the profiling I've done, the problem is that there is a dependency chain of instructions going on. Warps get stalled at the multiplication becasue they are dependent on the memory instruction to complete before they get to do anything. So we want to interleave independent instructions(this is handled by the unrolling) in order to minimize the stalling.
  5. Memory accesses are already coalesced from the original kernel. Since this streams into global memory, we aren't reusing data. Follows the same pattern as the original.

This was profiled on my 3080 and cuda 12.4.

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@ZelboK ZelboK changed the title [WIP] int8 quantization kernel refactoring & optimization [KERNEL] int8 quantization kernel refactoring & optimization WIP May 31, 2024
const int tid = threadIdx.x;
const int token_idx = blockIdx.x;
const float4* vectorized = reinterpret_cast<const float4*>(input);
const int traverse_space = hidden_size >> 2;
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just divides this by 4(since we're using float4 we need to do this as we're handling 4x as much work per iteration). Just avoiding the division assembly here.

for (int i = tid; i < hidden_size; i += blockDim.x) {
out[token_idx * hidden_size + i] =
float_to_int8_rn(((float)input[token_idx * hidden_size + i]) / scale);
#pragma unroll 4
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@ZelboK ZelboK May 31, 2024

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This will improve ILP by reordering the instructions a bit to reduce the impact of the warp stalling from the memory load operation.

It seems that manual unrolling might give a very slight advantage over the macro though. However for maintainability it might not be worth doing that.

@@ -48,12 +67,13 @@ void static_scaled_int8_quant(torch::Tensor& out, // [..., hidden_size]
int num_tokens = input.numel() / hidden_size;
dim3 grid(num_tokens);
dim3 block(std::min(hidden_size, 1024));
const float inverted_scale = 1.0f / scale;
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divide this on host so that we can use multiplication instructions instead of division in the kernel itself. Value is constant so works perfectly fine and simply.

@ZelboK
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ZelboK commented May 31, 2024

So for fp16 we would need to do something like...

    struct half4
    {
        half2 x, y; // 2 half2s since cuda doesn't support half4
    };
    
     template <>
    __global__ void static_scaled_int8_quant_kernel<half4, float>(
        const half4 *__restrict__ input, int8_t *__restrict__ out,
        float inverted_scale, const int hidden_size)
    {
    ... 
     unroll 4
        for (int i = tid; i < traverse_space; i += blockDim.x)
        {
            int index = token_idx * traverse_space + i;

            half4 data_half4 = vectorized[index];

            // Convert half2 to float
            float2 data0 = __half22float2(data_half4.x);
            float2 data1 = __half22float2(data_half4.y);
            ...

etc which can just be a specialization. Can experiment with overloading as well to see what impacts this has on compile times(if important) since we are introducing another kernel

@robertgshaw2-redhat
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Could you focus on the fp16 / bf16 case? We won’t run the fp32 activations very often

@ZelboK
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ZelboK commented May 31, 2024

Could you focus on the fp16 / bf16 case? We won’t run the fp32 activations very often

Yep that's fine with me. The code should mostly follow the same logic, will push when I get the chance!

pcmoritz pushed a commit that referenced this pull request Jun 12, 2024
Inspired by #5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large).

In details, we applied 3 optimizations:

- Use inverted scale so that most divisions are changed to multiplications.
- Unroll the loop by 4 times to improve ILP.
- Use vectorized 4 to transfer data between HBM and SRAM.
robertgshaw2-redhat pushed a commit to neuralmagic/nm-vllm that referenced this pull request Jun 16, 2024
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large).

In details, we applied 3 optimizations:

- Use inverted scale so that most divisions are changed to multiplications.
- Unroll the loop by 4 times to improve ILP.
- Use vectorized 4 to transfer data between HBM and SRAM.
joerunde pushed a commit to joerunde/vllm that referenced this pull request Jun 17, 2024
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large).

In details, we applied 3 optimizations:

- Use inverted scale so that most divisions are changed to multiplications.
- Unroll the loop by 4 times to improve ILP.
- Use vectorized 4 to transfer data between HBM and SRAM.
xjpang pushed a commit to xjpang/vllm that referenced this pull request Jun 27, 2024
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large).

In details, we applied 3 optimizations:

- Use inverted scale so that most divisions are changed to multiplications.
- Unroll the loop by 4 times to improve ILP.
- Use vectorized 4 to transfer data between HBM and SRAM.
xjpang pushed a commit to xjpang/vllm that referenced this pull request Jul 8, 2024
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large).

In details, we applied 3 optimizations:

- Use inverted scale so that most divisions are changed to multiplications.
- Unroll the loop by 4 times to improve ILP.
- Use vectorized 4 to transfer data between HBM and SRAM.
xjpang pushed a commit to xjpang/vllm that referenced this pull request Jul 24, 2024
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large).

In details, we applied 3 optimizations:

- Use inverted scale so that most divisions are changed to multiplications.
- Unroll the loop by 4 times to improve ILP.
- Use vectorized 4 to transfer data between HBM and SRAM.
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This pull request has been automatically marked as stale because it has not had any activity within 90 days. It will be automatically closed if no further activity occurs within 30 days. Leave a comment if you feel this pull request should remain open. Thank you!

@github-actions github-actions bot added the stale label Oct 26, 2024
@github-actions github-actions bot added unstale and removed stale labels Nov 27, 2024
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mergify bot commented Nov 27, 2024

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @ZelboK.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify mergify bot added the needs-rebase label Nov 27, 2024
@hmellor hmellor closed this Feb 18, 2025
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