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[KERNEL] int8 quantization kernel refactoring & optimization WIP #5146
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…loads & stores, alongside improving ILP
const int tid = threadIdx.x; | ||
const int token_idx = blockIdx.x; | ||
const float4* vectorized = reinterpret_cast<const float4*>(input); | ||
const int traverse_space = hidden_size >> 2; |
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just divides this by 4(since we're using float4
we need to do this as we're handling 4x as much work per iteration). Just avoiding the division assembly here.
for (int i = tid; i < hidden_size; i += blockDim.x) { | ||
out[token_idx * hidden_size + i] = | ||
float_to_int8_rn(((float)input[token_idx * hidden_size + i]) / scale); | ||
#pragma unroll 4 |
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This will improve ILP by reordering the instructions a bit to reduce the impact of the warp stalling from the memory load operation.
It seems that manual unrolling might give a very slight advantage over the macro though. However for maintainability it might not be worth doing that.
@@ -48,12 +67,13 @@ void static_scaled_int8_quant(torch::Tensor& out, // [..., hidden_size] | |||
int num_tokens = input.numel() / hidden_size; | |||
dim3 grid(num_tokens); | |||
dim3 block(std::min(hidden_size, 1024)); | |||
const float inverted_scale = 1.0f / scale; |
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divide this on host so that we can use multiplication instructions instead of division in the kernel itself. Value is constant so works perfectly fine and simply.
So for fp16 we would need to do something like...
etc which can just be a specialization. Can experiment with overloading as well to see what impacts this has on compile times(if important) since we are introducing another kernel |
Could you focus on the fp16 / bf16 case? We won’t run the fp32 activations very often |
Yep that's fine with me. The code should mostly follow the same logic, will push when I get the chance! |
Inspired by #5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large). In details, we applied 3 optimizations: - Use inverted scale so that most divisions are changed to multiplications. - Unroll the loop by 4 times to improve ILP. - Use vectorized 4 to transfer data between HBM and SRAM.
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large). In details, we applied 3 optimizations: - Use inverted scale so that most divisions are changed to multiplications. - Unroll the loop by 4 times to improve ILP. - Use vectorized 4 to transfer data between HBM and SRAM.
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large). In details, we applied 3 optimizations: - Use inverted scale so that most divisions are changed to multiplications. - Unroll the loop by 4 times to improve ILP. - Use vectorized 4 to transfer data between HBM and SRAM.
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large). In details, we applied 3 optimizations: - Use inverted scale so that most divisions are changed to multiplications. - Unroll the loop by 4 times to improve ILP. - Use vectorized 4 to transfer data between HBM and SRAM.
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large). In details, we applied 3 optimizations: - Use inverted scale so that most divisions are changed to multiplications. - Unroll the loop by 4 times to improve ILP. - Use vectorized 4 to transfer data between HBM and SRAM.
Inspired by vllm-project#5146, this PR improves FP8 quantize kernel by vectorizing data transfer to better utilize memory bandwidth. Microbenchmark shows that this improved kernel can achieve 1.0x-1.5x speedup (especially when hidden size is large). In details, we applied 3 optimizations: - Use inverted scale so that most divisions are changed to multiplications. - Unroll the loop by 4 times to improve ILP. - Use vectorized 4 to transfer data between HBM and SRAM.
This pull request has been automatically marked as stale because it has not had any activity within 90 days. It will be automatically closed if no further activity occurs within 30 days. Leave a comment if you feel this pull request should remain open. Thank you! |
This pull request has merge conflicts that must be resolved before it can be |
This refactors the int8 quantization kernel so that it will optimize
f32 -> i8
. However, please note that fp16 will require use ofhalf2
though. That can be done with some template specializations but for brevity I will leave that outside of this PR for now.fp32
, this will significantly increase memory throughput.This was profiled on my 3080 and cuda 12.4.
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