Merge pull request #1233 from taichi-ishitani/unassigned_variable_che…

…ck_for_generic_module_instance Enable unasigned variable check on instance of module specified by generic
veryl-lang · Feb 7, 2025 · 7893222 · 7893222
2 parents 304b938 + c8c32cc
commit 7893222
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Showing 2 changed files with 27 additions and 19 deletions.
diff --git a/crates/analyzer/src/handlers/check_var_ref.rs b/crates/analyzer/src/handlers/check_var_ref.rs
@@ -2,7 +2,7 @@ use crate::analyzer_error::AnalyzerError;
 use crate::attribute::Attribute as Attr;
 use crate::attribute::{AllowItem, CondTypeItem};
 use crate::attribute_table;
-use crate::symbol::{Direction, Symbol, SymbolId, SymbolKind, TypeKind};
+use crate::symbol::{Direction, GenericBoundKind, Symbol, SymbolId, SymbolKind, TypeKind};
 use crate::symbol_table;
 use crate::var_ref::{
     AssignDeclarationType, AssignPosition, AssignPositionType, AssignStatementBranchItemType,
@@ -673,24 +673,18 @@ impl VerylGrammarTrait for CheckVarRef<'_> {
                                     }
                                 }
                             }
-                            SymbolKind::GenericParameter(ref _x) => {
-                                // TODO
-                                // Restore the statement below after implementing the proto type
-                                // of the std synchnozier.
-                                // This proto type is required for the std async fifo module.
-
-                                //if let GenericBoundKind::Proto(ref x) = x.bound {
-                                //    if let Ok(symbol) =
-                                //        symbol_table::resolve((x, &symbol.found.namespace))
-                                //    {
-                                //        if let SymbolKind::ProtoModule(x) = symbol.found.kind {
-                                //            for port in &x.ports {
-                                //                ports.insert(port.name(), port.property());
-                                //            }
-                                //        }
-                                //    }
-                                //}
-                                port_unknown = true;
+                            SymbolKind::GenericParameter(ref x) => {
+                                if let GenericBoundKind::Proto(ref x) = x.bound {
+                                    if let Ok(symbol) =
+                                        symbol_table::resolve((x, &symbol.found.namespace))
+                                    {
+                                        if let SymbolKind::ProtoModule(x) = symbol.found.kind {
+                                            for port in &x.ports {
+                                                ports.insert(port.name(), port.property());
+                                            }
+                                        }
+                                    }
+                                }
                             }
                             SymbolKind::SystemVerilog => {
                                 port_unknown = true;

diff --git a/crates/analyzer/src/tests.rs b/crates/analyzer/src/tests.rs
@@ -2360,6 +2360,20 @@ fn unassign_variable() {
     let errors = analyze(code);
     assert!(errors.is_empty());
 
+    let code = r#"
+    proto module ProtoA (
+        i_a: input logic,
+    );
+
+    module ModuleB::<A: ProtoA> {
+        var a: logic;
+        inst u: A (i_a: a);
+    }
+    "#;
+
+    let errors = analyze(code);
+    assert!(matches!(errors[0], AnalyzerError::UnassignVariable { .. }));
+
     let code = r#"
     proto module ProtoA (
         o_a: output logic,