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Merge pull request #1507 from vhda/verilog/enum
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Verilog/enum
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@masatake
masatake authored Jul 17, 2017
2 parents 4d14afc + 9a43317 commit 5567535
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49 changes: 49 additions & 0 deletions Units/parser-verilog.r/systemverilog-class.d/expected.tags
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Original file line number Diff line number Diff line change
Expand Up @@ -18,12 +18,32 @@ b input.sv /^virtual function myfunc (a, b);$/;" p function:paramtest3.myfunc
c input.sv /^ logic c;$/;" r class:supertest
c input.sv /^extern virtual function test ext_func (c, d);$/;" p prototype:paramtest3.ext_func
c input.sv /^function test paramtest3::ext_func (c, d);$/;" p function:paramtest3.ext_func
const_local_logic input.sv /^ const local logic const_local_logic;$/;" r class:test_attributes
const_logic input.sv /^ const logic const_logic;$/;" r class:test_attributes
const_protected_logic input.sv /^ const protected logic const_protected_logic;$/;" r class:test_attributes
const_static_logic input.sv /^ const static logic const_static_logic;$/;" r class:test_attributes
d input.sv /^extern virtual function test ext_func (c, d);$/;" p prototype:paramtest3.ext_func
d input.sv /^function test paramtest3::ext_func (c, d);$/;" p function:paramtest3.ext_func
enum_bit1 input.sv /^ enum_bit1,$/;" c enum:test.enum_complex
enum_bit2 input.sv /^ enum_bit2='x,$/;" c enum:test.enum_complex
enum_bit3 input.sv /^ enum_bit3=2'b01,$/;" c enum:test.enum_complex
enum_bit4 input.sv /^ enum_bit4[0:10]=2'b10,$/;" c enum:test.enum_complex
enum_bit5 input.sv /^ enum_bit5 [9:0] = 2'b10 ,$/;" c enum:test.enum_complex
enum_complex input.sv /^ } enum_complex;$/;" E class:test
enum_const1 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var1
enum_const1 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var2
enum_const2 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var1
enum_const2 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var2
enum_simple input.sv /^ enum {enum_simple1, enum_simple2} enum_simple;$/;" E class:test
enum_simple1 input.sv /^ enum {enum_simple1, enum_simple2} enum_simple;$/;" c enum:test.enum_simple
enum_simple2 input.sv /^ enum {enum_simple1, enum_simple2} enum_simple;$/;" c enum:test.enum_simple
enum_var1 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" E class:test
enum_var2 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" E class:test
ext_func input.sv /^extern virtual function test ext_func (c, d);$/;" Q class:paramtest3
ext_func input.sv /^function test paramtest3::ext_func (c, d);$/;" f class:paramtest3
extern_func input.sv /^ extern virtual function void extern_func (input bit a, input b);$/;" Q class:test
fwrd_ref input.sv /^ extern virtual function bit fwrd_ref;$/;" Q class:supertest
local_logic input.sv /^ local logic local_logic;$/;" r class:test_attributes
mult input.sv /^ function mult (a, input b = 0);$/;" f class:supertest
mult input.sv /^ function mult (a, input b = 0);$/;" f class:test
myfunc input.sv /^virtual function myfunc (a, b);$/;" f class:paramtest3
Expand All @@ -43,6 +63,10 @@ paramtest3.ext_func.d input.sv /^function test paramtest3::ext_func (c, d);$/;"
paramtest3.myfunc input.sv /^virtual function myfunc (a, b);$/;" f class:paramtest3
paramtest3.myfunc.a input.sv /^virtual function myfunc (a, b);$/;" p function:paramtest3.myfunc
paramtest3.myfunc.b input.sv /^virtual function myfunc (a, b);$/;" p function:paramtest3.myfunc
protected_logic input.sv /^ protected logic protected_logic;$/;" r class:test_attributes
rand_logic input.sv /^ rand logic rand_logic;$/;" r class:test_attributes
randc_logic input.sv /^ randc logic randc_logic;$/;" r class:test_attributes
static_logic input.sv /^ static logic static_logic;$/;" r class:test_attributes
supertest input.sv /^class supertest extends test;$/;" C inherits:test
supertest.c input.sv /^ logic c;$/;" r class:supertest
supertest.fwrd_ref input.sv /^ extern virtual function bit fwrd_ref;$/;" Q class:supertest
Expand All @@ -52,9 +76,34 @@ supertest.mult.b input.sv /^ function mult (a, input b = 0);$/;" p function:s
test input.sv /^class test;$/;" C
test.a input.sv /^ reg a;$/;" r class:test
test.b input.sv /^ logic b;$/;" r class:test
test.enum_complex input.sv /^ } enum_complex;$/;" E class:test
test.enum_complex.enum_bit1 input.sv /^ enum_bit1,$/;" c enum:test.enum_complex
test.enum_complex.enum_bit2 input.sv /^ enum_bit2='x,$/;" c enum:test.enum_complex
test.enum_complex.enum_bit3 input.sv /^ enum_bit3=2'b01,$/;" c enum:test.enum_complex
test.enum_complex.enum_bit4 input.sv /^ enum_bit4[0:10]=2'b10,$/;" c enum:test.enum_complex
test.enum_complex.enum_bit5 input.sv /^ enum_bit5 [9:0] = 2'b10 ,$/;" c enum:test.enum_complex
test.enum_simple input.sv /^ enum {enum_simple1, enum_simple2} enum_simple;$/;" E class:test
test.enum_simple.enum_simple1 input.sv /^ enum {enum_simple1, enum_simple2} enum_simple;$/;" c enum:test.enum_simple
test.enum_simple.enum_simple2 input.sv /^ enum {enum_simple1, enum_simple2} enum_simple;$/;" c enum:test.enum_simple
test.enum_var1 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" E class:test
test.enum_var1.enum_const1 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var1
test.enum_var1.enum_const2 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var1
test.enum_var2 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" E class:test
test.enum_var2.enum_const1 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var2
test.enum_var2.enum_const2 input.sv /^ enum {enum_const1, enum_const2} enum_var1, enum_var2;$/;" c enum:test.enum_var2
test.extern_func input.sv /^ extern virtual function void extern_func (input bit a, input b);$/;" Q class:test
test.extern_func.a input.sv /^ extern virtual function void extern_func (input bit a, input b);$/;" p prototype:test.extern_func
test.extern_func.b input.sv /^ extern virtual function void extern_func (input bit a, input b);$/;" p prototype:test.extern_func
test.mult input.sv /^ function mult (a, input b = 0);$/;" f class:test
test.mult.a input.sv /^ function mult (a, input b = 0);$/;" p function:test.mult
test.mult.b input.sv /^ function mult (a, input b = 0);$/;" p function:test.mult
test_attributes input.sv /^class test_attributes;$/;" C
test_attributes.const_local_logic input.sv /^ const local logic const_local_logic;$/;" r class:test_attributes
test_attributes.const_logic input.sv /^ const logic const_logic;$/;" r class:test_attributes
test_attributes.const_protected_logic input.sv /^ const protected logic const_protected_logic;$/;" r class:test_attributes
test_attributes.const_static_logic input.sv /^ const static logic const_static_logic;$/;" r class:test_attributes
test_attributes.local_logic input.sv /^ local logic local_logic;$/;" r class:test_attributes
test_attributes.protected_logic input.sv /^ protected logic protected_logic;$/;" r class:test_attributes
test_attributes.rand_logic input.sv /^ rand logic rand_logic;$/;" r class:test_attributes
test_attributes.randc_logic input.sv /^ randc logic randc_logic;$/;" r class:test_attributes
test_attributes.static_logic input.sv /^ static logic static_logic;$/;" r class:test_attributes
21 changes: 21 additions & 0 deletions Units/parser-verilog.r/systemverilog-class.d/input.sv
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Expand Up @@ -8,6 +8,15 @@
class test;
reg a;
logic b;
enum {enum_simple1, enum_simple2} enum_simple;
enum {enum_const1, enum_const2} enum_var1, enum_var2;
enum bit [1:0] {
enum_bit1,
enum_bit2='x,
enum_bit3=2'b01,
enum_bit4[0:10]=2'b10,
enum_bit5 [9:0] = 2'b10 ,
} enum_complex;
function mult (a, input b = 0);
return a * b;
endfunction : mult
Expand Down Expand Up @@ -43,3 +52,15 @@ endclass : paramtest3

function test paramtest3::ext_func (c, d);
endfunction

class test_attributes;
static logic static_logic;
protected logic protected_logic;
local logic local_logic;
const static logic const_static_logic;
const protected logic const_protected_logic;
const local logic const_local_logic;
rand logic rand_logic;
randc logic randc_logic;
const logic const_logic;
endclass : test_attributes
6 changes: 6 additions & 0 deletions Units/parser-verilog.r/systemverilog-qualifiers.d/expected.tags
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Original file line number Diff line number Diff line change
@@ -1,3 +1,7 @@
auto_function input.sv /^function automatic auto_function (x);$/;" f
auto_function.x input.sv /^function automatic auto_function (x);$/;" p function:auto_function
auto_static input.sv /^function static auto_static (x);$/;" f
auto_static.x input.sv /^function static auto_static (x);$/;" p function:auto_static
ext_func input.sv /^extern function ext_func (x, y);$/;" Q
ext_func.x input.sv /^extern function ext_func (x, y);$/;" p prototype:ext_func
ext_func.y input.sv /^extern function ext_func (x, y);$/;" p prototype:ext_func
Expand Down Expand Up @@ -52,6 +56,8 @@ x input.sv /^extern pure virtual task ext_pure_virt_task (x);$/;" p prototype:ex
x input.sv /^extern static function ext_static_func (x, y);$/;" p prototype:ext_static_func
x input.sv /^extern static task ext_static_task (x, y);$/;" p prototype:ext_static_task
x input.sv /^extern task ext_task (x, y);$/;" p prototype:ext_task
x input.sv /^function automatic auto_function (x);$/;" p function:auto_function
x input.sv /^function static auto_static (x);$/;" p function:auto_static
x input.sv /^pure virtual function pure_virt_func (x);$/;" p prototype:pure_virt_func
x input.sv /^pure virtual local function pure_virt_local_func (x);$/;" p prototype:pure_virt_local_func
x input.sv /^pure virtual local task pure_virt_local_task (x);$/;" p prototype:pure_virt_local_task
Expand Down
6 changes: 6 additions & 0 deletions Units/parser-verilog.r/systemverilog-qualifiers.d/input.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -34,3 +34,9 @@ pure virtual static task pure_virt_static_task (x);
pure virtual protected task pure_virt_protected_task (x);

pure virtual local task pure_virt_local_task (x);

function automatic auto_function (x);
endfunction : auto_function

function static auto_static (x);
endfunction : auto_static
54 changes: 46 additions & 8 deletions Units/parser-verilog.r/systemverilog-typedef.d/expected.tags
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Original file line number Diff line number Diff line change
@@ -1,8 +1,46 @@
myType input.sv /^} myType;$/;" T
myType2 input.sv /^typedef classname#(paramvalue) myType2;$/;" T
type_class input.sv /^typedef class type_class;$/;" Q
type_enum input.sv /^typedef enum type_enum;$/;" T
type_interface_class input.sv /^typedef interface class type_interface_class;$/;" T
type_struct input.sv /^typedef struct type_struct;$/;" T
type_union input.sv /^typedef union type_union;$/;" T
type_unnamed input.sv /^typedef type_unnamed;$/;" T
A input.sv /^ A = 2'b00,$/;" c typedef:type_enum_bit_bus_defined_values
B input.sv /^ B = 2'b01,$/;" c typedef:type_enum_bit_bus_defined_values
C input.sv /^ C = 2'b10,$/;" c typedef:type_enum_bit_bus_defined_values
D input.sv /^ D = {1'b1, 1'b1}$/;" c typedef:type_enum_bit_bus_defined_values
W input.sv /^typedef enum bit {W, X} type_enum_bit;$/;" c typedef:type_enum_bit
X input.sv /^typedef enum bit {W, X} type_enum_bit;$/;" c typedef:type_enum_bit
Y input.sv /^typedef enum bit [1:0] {Y, Z} type_enum_bit2;$/;" c typedef:type_enum_bit2
Z input.sv /^typedef enum bit [1:0] {Y, Z} type_enum_bit2;$/;" c typedef:type_enum_bit2
cond0 input.sv /^ cond0 = 0, cond1 = 1, cond2 = 2$/;" c typedef:type_int_unsigned
cond1 input.sv /^ cond0 = 0, cond1 = 1, cond2 = 2$/;" c typedef:type_int_unsigned
cond2 input.sv /^ cond0 = 0, cond1 = 1, cond2 = 2$/;" c typedef:type_int_unsigned
fwd_type input.sv /^typedef fwd_type;$/;" Q
fwd_type_class input.sv /^typedef class fwd_type_class;$/;" Q
fwd_type_enum input.sv /^typedef enum fwd_type_enum;$/;" Q
fwd_type_interface_class input.sv /^typedef interface class fwd_type_interface_class;$/;" Q
fwd_type_struct input.sv /^typedef struct fwd_type_struct;$/;" Q
fwd_type_union input.sv /^typedef union fwd_type_union;$/;" Q
no input.sv /^typedef enum {no, yes} type_enum;$/;" c typedef:type_enum
type_bit input.sv /^typedef bit type_bit;$/;" T
type_bit_bus input.sv /^typedef bit [1:0] type_bit_bus;$/;" T
type_bit_bus_array input.sv /^typedef bit [1:0] type_bit_bus_array [2:0];$/;" T
type_class input.sv /^typedef classname#(paramvalue) type_class;$/;" T
type_enum input.sv /^typedef enum {no, yes} type_enum;$/;" T
type_enum.no input.sv /^typedef enum {no, yes} type_enum;$/;" c typedef:type_enum
type_enum.yes input.sv /^typedef enum {no, yes} type_enum;$/;" c typedef:type_enum
type_enum_bit input.sv /^typedef enum bit {W, X} type_enum_bit;$/;" T
type_enum_bit.W input.sv /^typedef enum bit {W, X} type_enum_bit;$/;" c typedef:type_enum_bit
type_enum_bit.X input.sv /^typedef enum bit {W, X} type_enum_bit;$/;" c typedef:type_enum_bit
type_enum_bit2 input.sv /^typedef enum bit [1:0] {Y, Z} type_enum_bit2;$/;" T
type_enum_bit2.Y input.sv /^typedef enum bit [1:0] {Y, Z} type_enum_bit2;$/;" c typedef:type_enum_bit2
type_enum_bit2.Z input.sv /^typedef enum bit [1:0] {Y, Z} type_enum_bit2;$/;" c typedef:type_enum_bit2
type_enum_bit_bus_defined_values input.sv /^} type_enum_bit_bus_defined_values;$/;" T
type_enum_bit_bus_defined_values.A input.sv /^ A = 2'b00,$/;" c typedef:type_enum_bit_bus_defined_values
type_enum_bit_bus_defined_values.B input.sv /^ B = 2'b01,$/;" c typedef:type_enum_bit_bus_defined_values
type_enum_bit_bus_defined_values.C input.sv /^ C = 2'b10,$/;" c typedef:type_enum_bit_bus_defined_values
type_enum_bit_bus_defined_values.D input.sv /^ D = {1'b1, 1'b1}$/;" c typedef:type_enum_bit_bus_defined_values
type_int_unsigned input.sv /^ } type_int_unsigned;$/;" T
type_int_unsigned.cond0 input.sv /^ cond0 = 0, cond1 = 1, cond2 = 2$/;" c typedef:type_int_unsigned
type_int_unsigned.cond1 input.sv /^ cond0 = 0, cond1 = 1, cond2 = 2$/;" c typedef:type_int_unsigned
type_int_unsigned.cond2 input.sv /^ cond0 = 0, cond1 = 1, cond2 = 2$/;" c typedef:type_int_unsigned
type_struct input.sv /^ } type_struct;$/;" T
type_struct_union input.sv /^ } type_struct_union;$/;" T
type_union input.sv /^ } type_union;$/;" T
type_union_packed input.sv /^ } type_union_packed;$/;" T
type_union_tagged input.sv /^ } type_union_tagged;$/;" T
yes input.sv /^typedef enum {no, yes} type_enum;$/;" c typedef:type_enum
58 changes: 49 additions & 9 deletions Units/parser-verilog.r/systemverilog-typedef.d/input.sv
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Original file line number Diff line number Diff line change
@@ -1,15 +1,55 @@
typedef enum type_enum;
typedef struct type_struct;
typedef union type_union;
typedef class type_class;
typedef interface class type_interface_class;
typedef type_unnamed;
typedef enum fwd_type_enum;
typedef struct fwd_type_struct;
typedef union fwd_type_union;
typedef class fwd_type_class;
typedef interface class fwd_type_interface_class;
typedef fwd_type;

typedef enum {no, yes} type_enum;
typedef enum bit {W, X} type_enum_bit;
typedef enum bit [1:0] {Y, Z} type_enum_bit2;

typedef struct {
real struct_real;
bit [1:0] struct_bit;
} type_struct;

typedef union {
real union_real;
bit [1:0] union_bit;
} type_union;

typedef union packed {
bit [1:0] union_bit1;
bit [1:0] union_bit2;
} type_union_packed;

typedef union tagged {
void Invalid;
int Valid;
} type_union_tagged;

typedef struct {
real struct_real;
union {
int i;
bit b;
} struct_union;
} type_struct_union;

typedef bit type_bit;
typedef bit [1:0] type_bit_bus;
typedef bit [1:0] type_bit_bus_array [2:0];

typedef enum int unsigned{
cond0 = 0, cond1 = 1, cond2 = 2
} type_int_unsigned;

typedef enum bit [1:0] {
A = 2'b00,
B = 2'b01,
C = 2'b10,
D = 2'b11
} myType;
D = {1'b1, 1'b1}
} type_enum_bit_bus_defined_values;

typedef classname#(paramvalue) myType2;
typedef classname#(paramvalue) type_class;
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