VZV on FZV

[sffc]

No description provided.

[sffc]

Assembly code of VZVComponents::get_unchecked:

Before:

0000000000033440 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33440:	48 8b 0f             	mov    (%rdi),%rcx
   33443:	8b 04 b1             	mov    (%rcx,%rsi,4),%eax
   33446:	48 8d 56 01          	lea    0x1(%rsi),%rdx
   3344a:	48 3b 57 08          	cmp    0x8(%rdi),%rdx
   3344e:	75 0c                	jne    3345c <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x1c>
   33450:	48 8b 57 18          	mov    0x18(%rdi),%rdx
   33454:	48 29 c2             	sub    %rax,%rdx
   33457:	48 03 47 10          	add    0x10(%rdi),%rax
   3345b:	c3                   	ret    
   3345c:	8b 54 b1 04          	mov    0x4(%rcx,%rsi,4),%edx
   33460:	48 29 c2             	sub    %rax,%rdx
   33463:	48 03 47 10          	add    0x10(%rdi),%rax
   33467:	c3                   	ret    
   33468:	0f 1f 84 00 00 00 00 	nopl   0x0(%rax,%rax,1)
   3346f:	00 

After:

0000000000033130 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33130:	55                   	push   %rbp
   33131:	41 57                	push   %r15
   33133:	41 56                	push   %r14
   33135:	41 55                	push   %r13
   33137:	41 54                	push   %r12
   33139:	53                   	push   %rbx
   3313a:	50                   	push   %rax
   3313b:	49 89 fe             	mov    %rdi,%r14
   3313e:	48 8b 2f             	mov    (%rdi),%rbp
   33141:	4c 8b 6f 08          	mov    0x8(%rdi),%r13
   33145:	4c 8b 7f 18          	mov    0x18(%rdi),%r15
   33149:	0f b6 5d 00          	movzbl 0x0(%rbp),%ebx
   3314d:	48 c7 04 24 00 00 00 	movq   $0x0,(%rsp)
   33154:	00 
   33155:	48 8d 34 2b          	lea    (%rbx,%rbp,1),%rsi
   33159:	48 83 c6 01          	add    $0x1,%rsi
   3315d:	48 89 e7             	mov    %rsp,%rdi
   33160:	48 89 da             	mov    %rbx,%rdx
   33163:	ff 15 e7 cd 00 00    	call   *0xcde7(%rip)        # 3ff50 <memcpy@GLIBC_2.14>
   33169:	48 85 db             	test   %rbx,%rbx
   3316c:	74 69                	je     331d7 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0xa7>
   3316e:	4c 8b 24 24          	mov    (%rsp),%r12
   33172:	4c 89 e8             	mov    %r13,%rax
   33175:	48 c1 e8 20          	shr    $0x20,%rax
   33179:	74 4d                	je     331c8 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x98>
   3317b:	4c 89 e8             	mov    %r13,%rax
   3317e:	31 d2                	xor    %edx,%edx
   33180:	48 f7 f3             	div    %rbx
   33183:	48 83 f8 02          	cmp    $0x2,%rax
   33187:	74 23                	je     331ac <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x7c>
   33189:	48 c7 04 24 00 00 00 	movq   $0x0,(%rsp)
   33190:	00 
   33191:	48 8d 34 5d 01 00 00 	lea    0x1(,%rbx,2),%rsi
   33198:	00 
   33199:	48 01 ee             	add    %rbp,%rsi
   3319c:	48 89 e7             	mov    %rsp,%rdi
   3319f:	48 89 da             	mov    %rbx,%rdx
   331a2:	ff 15 a8 cd 00 00    	call   *0xcda8(%rip)        # 3ff50 <memcpy@GLIBC_2.14>
   331a8:	4c 8b 3c 24          	mov    (%rsp),%r15
   331ac:	4d 29 e7             	sub    %r12,%r15
   331af:	4d 03 66 10          	add    0x10(%r14),%r12
   331b3:	4c 89 e0             	mov    %r12,%rax
   331b6:	4c 89 fa             	mov    %r15,%rdx
   331b9:	48 83 c4 08          	add    $0x8,%rsp
   331bd:	5b                   	pop    %rbx
   331be:	41 5c                	pop    %r12
   331c0:	41 5d                	pop    %r13
   331c2:	41 5e                	pop    %r14
   331c4:	41 5f                	pop    %r15
   331c6:	5d                   	pop    %rbp
   331c7:	c3                   	ret    
   331c8:	44 89 e8             	mov    %r13d,%eax
   331cb:	31 d2                	xor    %edx,%edx
   331cd:	f7 f3                	div    %ebx
   331cf:	48 83 f8 02          	cmp    $0x2,%rax
   331d3:	75 b4                	jne    33189 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x59>
   331d5:	eb d5                	jmp    331ac <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x7c>
   331d7:	48 8d 3d 22 44 00 00 	lea    0x4422(%rip),%rdi        # 37600 <str.0.118>
   331de:	48 8d 15 63 c9 00 00 	lea    0xc963(%rip),%rdx        # 3fb48 <__do_global_dtors_aux_fini_array_entry+0x1568>
   331e5:	be 19 00 00 00       	mov    $0x19,%esi
   331ea:	e8 d1 0f fd ff       	call   41c0 <_ZN4core9panicking5panic17h8705e81f284be8a5E>
   331ef:	0f 0b                	ud2    
   331f1:	66 2e 0f 1f 84 00 00 	cs nopw 0x0(%rax,%rax,1)
   331f8:	00 00 00 
   331fb:	0f 1f 44 00 00       	nopl   0x0(%rax,%rax,1)

Needless to say, it's a bit slower.

[sffc]

I got it to go a little bit faster by special-casing width=1 and width=2. It's still a slowdown unfortunately though.

vzv/overview            time:   [1.3772 us 1.3807 us 1.3846 us]                          
                        change: [+259.98% +262.45% +264.54%] (p = 0.00 < 0.05)
                        Performance has regressed.

vzv/char_count/slice    time:   [493.39 ns 494.29 ns 495.41 ns]                                  
                        change: [-4.2065% -3.7061% -3.3112%] (p = 0.00 < 0.05)
                        Performance has improved.

vzv/char_count/vzv      time:   [1.4575 us 1.4606 us 1.4637 us]                                
                        change: [+182.14% +183.00% +183.82%] (p = 0.00 < 0.05)
                        Performance has regressed.

vzv/binary_search/slice time:   [329.20 ns 331.03 ns 334.19 ns]                                    
                        change: [-0.6930% -0.1624% +0.6196%] (p = 0.66 > 0.05)
                        No change in performance detected.
Found 15 outliers among 100 measurements (15.00%)
  9 (9.00%) low mild
  3 (3.00%) high mild
  3 (3.00%) high severe

vzv/binary_search/vzv   time:   [426.23 ns 428.20 ns 430.52 ns]                                  
                        change: [+38.519% +39.430% +40.422%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 2 outliers among 100 measurements (2.00%)
  1 (1.00%) high mild
  1 (1.00%) high severe

vzv/binary_search/single/slice                                                                             
                        time:   [30.768 ns 30.867 ns 30.964 ns]
                        change: [-13.190% -7.5696% -3.2066%] (p = 0.00 < 0.05)
                        Performance has improved.
Found 1 outliers among 100 measurements (1.00%)
  1 (1.00%) high severe

vzv/binary_search/single/vzv                                                                             
                        time:   [40.876 ns 41.021 ns 41.199 ns]
                        change: [+32.107% +40.255% +49.616%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 13 outliers among 100 measurements (13.00%)
  9 (9.00%) high mild
  4 (4.00%) high severe

vzv_precompute/get/precomputed                                                                             
                        time:   [2.1330 ns 2.1367 ns 2.1419 ns]
                        change: [+127.60% +129.27% +130.84%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 6 outliers among 100 measurements (6.00%)
  3 (3.00%) high mild
  3 (3.00%) high severe

vzv_precompute/get/slice                                                                             
                        time:   [2.3687 ns 2.3740 ns 2.3792 ns]
                        change: [+122.45% +124.15% +125.66%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 8 outliers among 100 measurements (8.00%)
  2 (2.00%) low mild
  3 (3.00%) high mild
  3 (3.00%) high severe

vzv_precompute/search/precomputed                                                                             
                        time:   [37.914 ns 38.018 ns 38.127 ns]
                        change: [+15.567% +17.514% +19.263%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 1 outliers among 100 measurements (1.00%)
  1 (1.00%) high mild

vzv_precompute/search/slice                                                                             
                        time:   [40.217 ns 40.328 ns 40.444 ns]
                        change: [+24.757% +25.261% +25.793%] (p = 0.00 < 0.05)
                        Performance has regressed.

vzv_precompute/search_multi/precomputed                                                                            
                        time:   [394.69 ns 402.56 ns 411.46 ns]
                        change: [+25.289% +26.806% +28.462%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 17 outliers among 100 measurements (17.00%)
  4 (4.00%) high mild
  13 (13.00%) high severe

vzv_precompute/search_multi/slice                                                                            
                        time:   [366.00 ns 367.15 ns 368.37 ns]
                        change: [+19.280% +19.728% +20.178%] (p = 0.00 < 0.05)
                        Performance has regressed.
Found 11 outliers among 100 measurements (11.00%)
  10 (10.00%) high mild
  1 (1.00%) high severe

[sffc]

Trying to narrow down the root cause.

Some more info:

• Baseline performance: ~1.0 ns. Performance on branch: ~2.0 ns.
• If I replace the implementation of FlexZeroSlice::get_unchecked to always assume an index width of 2 (the width used in the bench), I get ~1.6 ns.
• As soon as I replace the indices ULE array with a FlexZeroSlice, even if I don't use any features of FlexZeroSlice, I go from ~1.0 ns to ~1.6 ns. See third commit in this branch: https://github.com/sffc/omnicu/tree/vzv-cleanup

[sffc]

Additional findings:

• Replacing the &[RawBytesULE<>] field in VZVComponents with &[u8] regresses from ~1.0 ns to ~1.2 ns
• Replacing it with &FlexZeroSlice, but using no FVS machinery, has no regression
• Calculating .len() from FZS regresses from ~1.2 ns to ~1.6 ns

So, here's the summary of my findings:

Item	Penalty
Store &[u8] instead of &[RawBytesULE<>]	~0.2 ns
Calculate length using variable width field	~0.4 ns
Branch on width when fetching element	~0.4 ns

[sffc]

Possible next step: change the VarZeroVec index array to store the endpoints instead of the startpoints of each range. For example, right now we store [0, 3, 5, 8], but we should instead store [3, 5, 8, 12]. Doing so means that we can check if index == 0 instead of if index == self.indices.len(), and eliminate the (now expensive) call to .len().

[sffc]

Assembly code across 76c6f24:

0000000000033440 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33440:	48 8b 0f             	mov    (%rdi),%rcx
   33443:	8b 04 b1             	mov    (%rcx,%rsi,4),%eax
   33446:	48 8d 56 01          	lea    0x1(%rsi),%rdx
   3344a:	48 3b 57 08          	cmp    0x8(%rdi),%rdx
   3344e:	75 0c                	jne    3345c <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x1c>
   33450:	48 8b 57 18          	mov    0x18(%rdi),%rdx
   33454:	48 29 c2             	sub    %rax,%rdx
   33457:	48 03 47 10          	add    0x10(%rdi),%rax
   3345b:	c3                   	ret    
   3345c:	8b 54 b1 04          	mov    0x4(%rcx,%rsi,4),%edx
   33460:	48 29 c2             	sub    %rax,%rdx
   33463:	48 03 47 10          	add    0x10(%rdi),%rax
   33467:	c3                   	ret    
   33468:	0f 1f 84 00 00 00 00 	nopl   0x0(%rax,%rax,1)
   3346f:	00 

to

0000000000033440 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33440:	4c 8b 07             	mov    (%rdi),%r8
   33443:	48 8b 57 08          	mov    0x8(%rdi),%rdx
   33447:	48 c1 ea 02          	shr    $0x2,%rdx
   3344b:	41 8b 04 b0          	mov    (%r8,%rsi,4),%eax
   3344f:	48 8d 4e 01          	lea    0x1(%rsi),%rcx
   33453:	48 39 d1             	cmp    %rdx,%rcx
   33456:	75 0c                	jne    33464 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x24>
   33458:	48 8b 57 18          	mov    0x18(%rdi),%rdx
   3345c:	48 29 c2             	sub    %rax,%rdx
   3345f:	48 03 47 10          	add    0x10(%rdi),%rax
   33463:	c3                   	ret    
   33464:	41 8b 54 b0 04       	mov    0x4(%r8,%rsi,4),%edx
   33469:	48 29 c2             	sub    %rax,%rdx
   3346c:	48 03 47 10          	add    0x10(%rdi),%rax
   33470:	c3                   	ret    
   33471:	66 2e 0f 1f 84 00 00 	cs nopw 0x0(%rax,%rax,1)
   33478:	00 00 00 
   3347b:	0f 1f 44 00 00       	nopl   0x0(%rax,%rax,1)

and across 36fdb8d to

0000000000033440 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33440:	4c 8b 07             	mov    (%rdi),%r8
   33443:	48 8b 57 08          	mov    0x8(%rdi),%rdx
   33447:	48 83 c2 ff          	add    $0xffffffffffffffff,%rdx
   3344b:	48 c1 ea 02          	shr    $0x2,%rdx
   3344f:	41 8b 44 b0 01       	mov    0x1(%r8,%rsi,4),%eax
   33454:	48 8d 4e 01          	lea    0x1(%rsi),%rcx
   33458:	48 39 d1             	cmp    %rdx,%rcx
   3345b:	75 0c                	jne    33469 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x29>
   3345d:	48 8b 57 18          	mov    0x18(%rdi),%rdx
   33461:	48 29 c2             	sub    %rax,%rdx
   33464:	48 03 47 10          	add    0x10(%rdi),%rax
   33468:	c3                   	ret    
   33469:	41 8b 54 b0 05       	mov    0x5(%r8,%rsi,4),%edx
   3346e:	48 29 c2             	sub    %rax,%rdx
   33471:	48 03 47 10          	add    0x10(%rdi),%rax
   33475:	c3                   	ret    
   33476:	66 2e 0f 1f 84 00 00 	cs nopw 0x0(%rax,%rax,1)
   3347d:	00 00 00 

and across daec8eb

0000000000033110 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33110:	50                   	push   %rax
   33111:	48 8b 4f 08          	mov    0x8(%rdi),%rcx
   33115:	48 85 c9             	test   %rcx,%rcx
   33118:	74 34                	je     3314e <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x3e>
   3311a:	4c 8b 07             	mov    (%rdi),%r8
   3311d:	48 83 c1 ff          	add    $0xffffffffffffffff,%rcx
   33121:	48 c1 e9 02          	shr    $0x2,%rcx
   33125:	41 8b 44 b0 01       	mov    0x1(%r8,%rsi,4),%eax
   3312a:	48 8d 56 01          	lea    0x1(%rsi),%rdx
   3312e:	48 39 ca             	cmp    %rcx,%rdx
   33131:	75 0d                	jne    33140 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x30>
   33133:	48 8b 57 18          	mov    0x18(%rdi),%rdx
   33137:	48 29 c2             	sub    %rax,%rdx
   3313a:	48 03 47 10          	add    0x10(%rdi),%rax
   3313e:	59                   	pop    %rcx
   3313f:	c3                   	ret    
   33140:	41 8b 54 b0 05       	mov    0x5(%r8,%rsi,4),%edx
   33145:	48 29 c2             	sub    %rax,%rdx
   33148:	48 03 47 10          	add    0x10(%rdi),%rax
   3314c:	59                   	pop    %rcx
   3314d:	c3                   	ret    
   3314e:	48 8d 3d c3 44 00 00 	lea    0x44c3(%rip),%rdi        # 37618 <str.5+0x918>
   33155:	48 8d 15 ec c9 00 00 	lea    0xc9ec(%rip),%rdx        # 3fb48 <__do_global_dtors_aux_fini_array_entry+0x1568>
   3315c:	be 19 00 00 00       	mov    $0x19,%esi
   33161:	e8 5a 10 fd ff       	call   41c0 <_ZN4core9panicking5panic17h8705e81f284be8a5E>
   33166:	0f 0b                	ud2    
   33168:	0f 1f 84 00 00 00 00 	nopl   0x0(%rax,%rax,1)

and across bfd450f

0000000000033110 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33110:	4c 8b 07             	mov    (%rdi),%r8
   33113:	48 8b 57 08          	mov    0x8(%rdi),%rdx
   33117:	48 c1 ea 02          	shr    $0x2,%rdx
   3311b:	41 8b 44 b0 01       	mov    0x1(%r8,%rsi,4),%eax
   33120:	48 8d 4e 01          	lea    0x1(%rsi),%rcx
   33124:	48 39 d1             	cmp    %rdx,%rcx
   33127:	75 0c                	jne    33135 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x25>
   33129:	48 8b 57 18          	mov    0x18(%rdi),%rdx
   3312d:	48 29 c2             	sub    %rax,%rdx
   33130:	48 03 47 10          	add    0x10(%rdi),%rax
   33134:	c3                   	ret    
   33135:	41 8b 54 b0 05       	mov    0x5(%r8,%rsi,4),%edx
   3313a:	48 29 c2             	sub    %rax,%rdx
   3313d:	48 03 47 10          	add    0x10(%rdi),%rax
   33141:	c3                   	ret    
   33142:	66 2e 0f 1f 84 00 00 	cs nopw 0x0(%rax,%rax,1)
   33149:	00 00 00 
   3314c:	0f 1f 40 00          	nopl   0x0(%rax)

and then across c548800

0000000000033110 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E>:
   33110:	50                   	push   %rax
   33111:	4c 8b 0f             	mov    (%rdi),%r9
   33114:	45 0f b6 19          	movzbl (%r9),%r11d
   33118:	4d 85 db             	test   %r11,%r11
   3311b:	74 44                	je     33161 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x51>
   3311d:	41 8b 4c b1 01       	mov    0x1(%r9,%rsi,4),%ecx
   33122:	4c 8d 56 01          	lea    0x1(%rsi),%r10
   33126:	48 8b 47 08          	mov    0x8(%rdi),%rax
   3312a:	4c 8b 47 18          	mov    0x18(%rdi),%r8
   3312e:	48 89 c2             	mov    %rax,%rdx
   33131:	48 c1 ea 20          	shr    $0x20,%rdx
   33135:	74 1e                	je     33155 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x45>
   33137:	31 d2                	xor    %edx,%edx
   33139:	49 f7 f3             	div    %r11
   3313c:	49 39 c2             	cmp    %rax,%r10
   3313f:	74 05                	je     33146 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x36>
   33141:	45 8b 44 b1 05       	mov    0x5(%r9,%rsi,4),%r8d
   33146:	49 29 c8             	sub    %rcx,%r8
   33149:	48 03 4f 10          	add    0x10(%rdi),%rcx
   3314d:	48 89 c8             	mov    %rcx,%rax
   33150:	4c 89 c2             	mov    %r8,%rdx
   33153:	59                   	pop    %rcx
   33154:	c3                   	ret    
   33155:	31 d2                	xor    %edx,%edx
   33157:	41 f7 f3             	div    %r11d
   3315a:	49 39 c2             	cmp    %rax,%r10
   3315d:	75 e2                	jne    33141 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x31>
   3315f:	eb e5                	jmp    33146 <_ZN7zerovec10varzerovec10components29VarZeroVecComponents$LT$T$GT$13get_unchecked17hf9a537bad03d45f6E+0x36>
   33161:	48 8d 3d 48 45 00 00 	lea    0x4548(%rip),%rdi        # 376b0 <str.0.118>
   33168:	48 8d 15 d9 c9 00 00 	lea    0xc9d9(%rip),%rdx        # 3fb48 <__do_global_dtors_aux_fini_array_entry+0x1580>
   3316f:	be 19 00 00 00       	mov    $0x19,%esi
   33174:	e8 47 10 fd ff       	call   41c0 <_ZN4core9panicking5panic17h8705e81f284be8a5E>
   33179:	0f 0b                	ud2    
   3317b:	0f 1f 44 00 00       	nopl   0x0(%rax,%rax,1)

[sffc]

This is superseded by VarZeroVecFormat; see #1410 and #2312