Chisel 3.5 Bump

[abejgonzalez]

This PR is adapted from #150 and also removes some warnings from elaboration.

Must be merged alongside ucb-bar/chipyard#1060

[hngenc]

Just FYI, we added our own def fire(dummy: Int=0): Bool methods to a lot of our own custom bundles.

I'm not sure if those will compile with your latest change

[abejgonzalez]

Just FYI, we added our own def fire(dummy: Int=0): Bool methods to a lot of our own custom bundles.

I'm not sure if those will compile with your latest change

So far this PR seems to generate Verilog properly. Lets see what the CI in Chipyard says.