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Add PD-optimized variant of boom #1816

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Mar 9, 2024
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17 changes: 10 additions & 7 deletions .github/scripts/defaults.sh
Original file line number Diff line number Diff line change
Expand Up @@ -28,11 +28,11 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache

# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"

Expand All @@ -47,8 +47,10 @@ mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig"
mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig verilog"
mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
mapping["chipyard-boom"]=" CONFIG=MediumBoomCosimConfig"
mapping["chipyard-dmiboom"]=" CONFIG=dmiMediumBoomCosimConfig"
mapping["chipyard-boomv3"]=" CONFIG=MediumBoomV3CosimConfig"
mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
Expand All @@ -60,10 +62,11 @@ mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness
mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
mapping["chipyard-symmetric"]=" CONFIG=MultiSimSymmetricChipletRocketConfig"
mapping["chipyard-llcchiplet"]=" CONFIG=MultiSimLLCChipletRocketConfig"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomV3Config verilog"
mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
mapping["tracegen-boomv3"]=" CONFIG=BoomV3TraceGenConfig"
mapping["tracegen-boomv4"]=" CONFIG=BoomV4TraceGenConfig"
mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
Expand Down
17 changes: 14 additions & 3 deletions .github/scripts/run-tests.sh
Original file line number Diff line number Diff line change
Expand Up @@ -46,13 +46,21 @@ case $1 in
$LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
;;
chipyard-boom)
chipyard-boomv3)
run_bmark
;;
chipyard-boomv4)
run_bmark
;;
chipyard-shuttle)
run_bmark ${mapping[$1]}
;;
chipyard-dmiboom)
chipyard-dmiboomv3)
# Test checkpoint-restore
$LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
;;
chipyard-dmiboomv4)
# Test checkpoint-restore
$LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
Expand Down Expand Up @@ -129,7 +137,10 @@ case $1 in
tracegen)
run_tracegen
;;
tracegen-boom)
tracegen-boomv3)
run_tracegen
;;
tracegen-boomv4)
run_tracegen
;;
chipyard-cva6)
Expand Down
96 changes: 84 additions & 12 deletions .github/workflows/chipyard-run-tests.yml
Original file line number Diff line number Diff line change
Expand Up @@ -455,8 +455,8 @@ jobs:
group-key: "group-cores"
project-key: "chipyard-hetero"

chipyard-boom-run-tests:
name: chipyard-boom-run-tests
chipyard-boomv3-run-tests:
name: chipyard-boomv3-run-tests
needs: prepare-chipyard-cores
runs-on: as4
steps:
Expand All @@ -476,7 +476,30 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-boom"
project-key: "chipyard-boomv3"

chipyard-boomv4-run-tests:
name: chipyard-boomv4-run-tests
needs: prepare-chipyard-cores
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v4
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-boomv4"

chipyard-shuttle-run-tests:
name: chipyard-shuttle-run-tests
Expand Down Expand Up @@ -616,8 +639,8 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-dmirocket"

chipyard-dmiboom-run-tests:
name: chipyard-dmiboom-run-tests
chipyard-dmiboomv3-run-tests:
name: chipyard-dmiboomv3-run-tests
needs: prepare-chipyard-peripherals
runs-on: as4
steps:
Expand All @@ -637,7 +660,30 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-peripherals"
project-key: "chipyard-dmiboom"
project-key: "chipyard-dmiboomv3"

chipyard-dmiboomv4-run-tests:
name: chipyard-dmiboomv4-run-tests
needs: prepare-chipyard-peripherals
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v4
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-peripherals"
project-key: "chipyard-dmiboomv4"

chipyard-spiflashwrite-run-tests:
name: chipyard-spiflashwrite-run-tests
Expand Down Expand Up @@ -870,8 +916,8 @@ jobs:
project-key: "chipyard-mempress"


tracegen-boom-run-tests:
name: tracegen-boom-run-tests
tracegen-boomv3-run-tests:
name: tracegen-boomv3-run-tests
needs: prepare-chipyard-tracegen
runs-on: as4
steps:
Expand All @@ -891,7 +937,30 @@ jobs:
uses: ./.github/actions/run-tests
with:
group-key: "group-tracegen"
project-key: "tracegen-boom"
project-key: "tracegen-boomv3"

tracegen-boomv4-run-tests:
name: tracegen-boomv4-run-tests
needs: prepare-chipyard-tracegen
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v4
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-tracegen"
project-key: "tracegen-boomv4"

tracegen-run-tests:
name: tracegen-run-tests
Expand Down Expand Up @@ -1107,12 +1176,14 @@ jobs:
documentation-check,
chipyard-rocket-run-tests,
chipyard-hetero-run-tests,
chipyard-boom-run-tests,
chipyard-boomv3-run-tests,
chipyard-boomv4-run-tests,
chipyard-shuttle-run-tests,
chipyard-cva6-run-tests,
chipyard-ibex-run-tests,
chipyard-sodor-run-tests,
chipyard-dmiboom-run-tests,
chipyard-dmiboomv3-run-tests,
chipyard-dmiboomv4-run-tests,
chipyard-dmirocket-run-tests,
chipyard-spiflashwrite-run-tests,
chipyard-manyperipherals-run-tests,
Expand All @@ -1125,7 +1196,8 @@ jobs:
chipyard-prefetchers-run-tests,
chipyard-mempress-run-tests,
chipyard-constellation-run-tests,
tracegen-boom-run-tests,
tracegen-boomv3-run-tests,
tracegen-boomv4-run-tests,
tracegen-run-tests,
icenet-run-tests,
testchipip-run-tests,
Expand Down
2 changes: 1 addition & 1 deletion docs/Simulation/FPGA-Accelerated-Simulation.rst
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ A FireSim simulation requires 3 additional config fragments:


The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme.
After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.
After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomV3Config`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomV3Config``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name.

An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments.
We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``.
Expand Down
2 changes: 1 addition & 1 deletion fpga/src/main/scala/vc707/Configs.scala
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ class RocketVC707Config extends Config (
class BoomVC707Config extends Config (
new WithFPGAFrequency(50) ++
new WithVC707Tweaks ++
new chipyard.MegaBoomConfig
new chipyard.MegaBoomV3Config
)

class WithFPGAFrequency(fMHz: Double) extends Config (
Expand Down
2 changes: 1 addition & 1 deletion fpga/src/main/scala/vcu118/Configs.scala
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ class RocketVCU118Config extends Config(
class BoomVCU118Config extends Config(
new WithFPGAFrequency(50) ++
new WithVCU118Tweaks ++
new chipyard.MegaBoomConfig
new chipyard.MegaBoomV3Config
)

class WithFPGAFrequency(fMHz: Double) extends Config(
Expand Down
2 changes: 1 addition & 1 deletion generators/boom
Submodule boom updated 122 files
6 changes: 2 additions & 4 deletions generators/chipyard/src/main/scala/Subsystem.scala
Original file line number Diff line number Diff line change
Expand Up @@ -20,9 +20,6 @@ import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._

import boom.common.{BoomTile}


import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}

trait CanHaveHTIF { this: BaseSubsystem =>
Expand Down Expand Up @@ -83,7 +80,8 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
{
def coreMonitorBundles = totalTiles.values.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle
case b: boom.v3.common.BoomTile => b.module.core.coreMonitorBundle
case b: boom.v4.common.BoomTile => b.module.core.coreMonitorBundle
}.toList

// No-tile configs have to be handled specially.
Expand Down
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