Add debug clock tap port to all default designs

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -33,6 +33,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
   with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
   with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
+  with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
   with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
   with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
 {

generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala

@@ -0,0 +1,32 @@
+package chipyard.clocking
+
+import chisel3._
+
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.prci._
+
+case class ClockTapParams(
+  busWhere: TLBusWrapperLocation = SBUS, // by default, tap the sbus clock as a debug clock
+  divider: Int = 16, // a fixed clock division ratio for the clock tap
+)
+
+case object ClockTapKey extends Field[Option[ClockTapParams]](Some(ClockTapParams()))
+
+trait CanHaveClockTap { this: BaseSubsystem =>
+  val clockTapNode = p(ClockTapKey).map { tapParams =>
+    val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
+    val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider))
+    clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode
+    clockTap
+  }
+  val clockTapIO = clockTapNode.map { node => InModuleBody {
+    val clock_tap = IO(Output(Clock()))
+    clock_tap := node.in.head._1.clock
+    clock_tap
+  }}
+}

generators/chipyard/src/main/scala/clocking/ClockBinders.scala

@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 import chisel3.util._
-import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey, ClockPort, ResetPort}
+import chipyard.iobinders._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.subsystem._
@@ -119,3 +119,12 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
     }
   }
 })
+
+class WithClockTapIOCells extends OverrideIOBinder({
+  (system: CanHaveClockTap) => {
+    system.clockTapIO.map { tap =>
+      val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
+      (Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
+    }.getOrElse((Nil, Nil))
+  }
+})

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -51,9 +51,10 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithUARTTSIPunchthrough ++
   new chipyard.iobinders.WithNMITiedOff ++
 
-  // By default, punch out IOs to the Harness
-  new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
+  new chipyard.clocking.WithClockTapIOCells ++                      // Default generate a clock tapio
+  new chipyard.clocking.WithPassthroughClockGenerator ++            // Default punch out IOs to the Harness
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore",    // Default merge all the bus clocks
+    Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
   new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus
 

generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala

@@ -122,3 +122,7 @@ class WithNoTileResetSetters extends Config((site, here, up) => {
 class WithNoResetSynchronizers extends Config((site, here, up) => {
   case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
 })
+
+class WithNoClockTap extends Config((site, here, up) => {
+  case ClockTapKey => None
+})

generators/chipyard/src/main/scala/iobinders/Ports.scala

@@ -86,6 +86,9 @@ case class CustomBootPort  (val getIO: () => Bool)
 case class ClockPort       (val getIO: () => Clock, val freqMHz: Double)
     extends Port[Clock]
 
+case class ClockTapPort    (val getIO: () => Clock)
+    extends Port[Clock]
+
 case class ResetPort       (val getIO: () => AsyncReset)
     extends Port[Reset]
 

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -84,6 +84,7 @@ class WithMinimalFireSimDesignTweaks extends Config(
   new chipyard.harness.WithHarnessBinderClockFreqMHz(1000.0) ++
   new chipyard.harness.WithClockFromHarness ++
   new chipyard.harness.WithResetFromHarness ++
+  new chipyard.config.WithNoClockTap ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
   // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
   new WithBootROM ++
@@ -98,6 +99,8 @@ class WithMinimalFireSimDesignTweaks extends Config(
 // Non-frequency tweaks that are generally applied to all firesim configs
 class WithFireSimDesignTweaks extends Config(
   new WithMinimalFireSimDesignTweaks ++
+  // Required: Remove the debug clock tap, this breaks compilation of target-level sim in FireSim
+  new chipyard.config.WithNoClockTap ++
   // Required: Bake in the default FASED memory model
   new WithDefaultMemModel ++
   // Optional: reduce the width of the Serial TL interface