Move clock tap to its own async domain

ucb-bar · Dec 18, 2023 · 9942d95 · 9942d95
1 parent 2f10122
commit 9942d95
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Showing 3 changed files with 6 additions and 11 deletions.
diff --git a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
@@ -10,18 +10,13 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
-case class ClockTapParams(
-  busWhere: TLBusWrapperLocation = SBUS, // by default, tap the sbus clock as a debug clock
-  divider: Int = 16, // a fixed clock division ratio for the clock tap
-)
-
-case object ClockTapKey extends Field[Option[ClockTapParams]](Some(ClockTapParams()))
+case object ClockTapKey extends Field[Boolean](true)
 
 trait CanHaveClockTap { this: BaseSubsystem =>
-  val clockTapNode = p(ClockTapKey).map { tapParams =>
+  require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
+  val clockTapNode = Option.when(p(ClockTapKey)) {
     val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
-    val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider))
-    clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode
+    clockTap := ClockGroup() := asyncClockGroupsNode
     clockTap
   }
   val clockTapIO = clockTapNode.map { node => InModuleBody {

diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -54,7 +54,7 @@ class AbstractConfig extends Config(
   new chipyard.clocking.WithClockTapIOCells ++                      // Default generate a clock tapio
   new chipyard.clocking.WithPassthroughClockGenerator ++            // Default punch out IOs to the Harness
   new chipyard.clocking.WithClockGroupsCombinedByName(("uncore",    // Default merge all the bus clocks
-    Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
+    Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
   new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus
   new chipyard.config.WithControlBusFrequency(500.0) ++             // Default 500 MHz cbus

diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -130,5 +130,5 @@ class WithNoResetSynchronizers extends Config((site, here, up) => {
 
 // Remove any ClockTap ports in this system
 class WithNoClockTap extends Config((site, here, up) => {
-  case ClockTapKey => None
+  case ClockTapKey => false
 })