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fix macro anno error #34

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fix macro anno error #34

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c8552fd
fix anno error
donggyukim May 4, 2018
e91e3f8
match port names
donggyukim May 7, 2018
d3966db
properly initialize macro ports
donggyukim Sep 7, 2018
d88ef13
collect magic
donggyukim Sep 7, 2018
707014a
[bugfix] fix broken read enables
donggyukim Sep 16, 2018
a188315
[bugfix] fix mask bit overflow condition
donggyukim Oct 7, 2018
afb2188
[bugfix] read only ports can have chip enables
donggyukim Oct 7, 2018
89835d2
[bugfix] fix default cost metric
donggyukim Oct 8, 2018
67eddb3
[bugfix] correctly connect chip enable of read-only port
donggyukim Oct 8, 2018
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12 changes: 9 additions & 3 deletions macros/src/main/scala/MacroCompiler.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -298,6 +298,13 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
val name = s"mem_${i}_${j}"
// Create the instance.
stmts += WDefInstance(NoInfo, name, lib.src.name, lib.tpe)
stmts ++= lib.sortedPorts flatMap { port =>
port.ports flatMap (p => p.direction match {
case Input =>
Some(IsInvalid(NoInfo, WSubField(WRef(name), p.name)))
case Output => None
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This looks like a good place for collect!

ports.collect { case Port(_, pname, Input, _) => IsInvalid(NoInfo, WSubField(WRef(name), pname)) }

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!

})
}
// Connect extra ports of the lib.
stmts ++= lib.extraPorts map { case (portName, portValue) =>
Connect(NoInfo, WSubField(WRef(name), portName), portValue)
Expand Down Expand Up @@ -707,7 +714,7 @@ object MacroCompiler extends App {
// Note: the last macro in the input list is (seemingly arbitrarily)
// determined as the firrtl "top-level module".
val circuit = Circuit(NoInfo, macros, macros.last.name)
val annotations = AnnotationMap(
val annotations =
Seq(MacroCompilerAnnotation(
circuit.main,
MacroCompilerAnnotation.Params(
Expand All @@ -717,8 +724,7 @@ object MacroCompiler extends App {
params.contains(UseCompiler)
)
))
)
val state = CircuitState(circuit, HighForm, Some(annotations))
val state = CircuitState(circuit, HighForm, annotations)

// Run the compiler.
val result = new MacroCompiler().compileAndEmit(state)
Expand Down
38 changes: 19 additions & 19 deletions macros/src/main/scala/SynFlops.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -32,9 +32,9 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
lib.src.depth,
1, // writeLatency
1, // readLatency. This is possible because of VerilogMemDelays
lib.readers.indices map (i => s"R_$i"),
lib.writers.indices map (i => s"W_$i"),
lib.readwriters.indices map (i => s"RW_$i")
lib.readers.indices map (i => s"R$i"),
lib.writers.indices map (i => s"W$i"),
lib.readwriters.indices map (i => s"RW$i")
)

val readConnects = lib.readers.zipWithIndex flatMap { case (r, i) =>
Expand All @@ -48,16 +48,16 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
case (None, Some(re_port)) => portToExpression(re_port)
case (None, None) => one
}
val data = memPortField(mem, s"R_$i", "data")
val data = memPortField(mem, s"R$i", "data")
val read = (dataType: @unchecked) match {
case VectorType(tpe, size) => cat(((0 until size) map (k =>
WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse)
case _: UIntType => data
}
Seq(
Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable),
Connect(NoInfo, memPortField(mem, s"R$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"R$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"R$i", "en"), enable),
Connect(NoInfo, WRef(r.src.output.get.name), read)
)
}
Expand All @@ -73,13 +73,13 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
case (None, Some(we)) => portToExpression(we)
case (None, None) => zero // is it possible?
}
val mask = memPortField(mem, s"W_$i", "mask")
val data = memPortField(mem, s"W_$i", "data")
val mask = memPortField(mem, s"W$i", "mask")
val data = memPortField(mem, s"W$i", "data")
val write = portToExpression(w.src.input.get)
Seq(
Connect(NoInfo, memPortField(mem, s"W_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"W_$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"W_$i", "en"), enable)
Connect(NoInfo, memPortField(mem, s"W$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"W$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"W$i", "en"), enable)
) ++ (dataType match {
case VectorType(tpe, size) =>
val width = bitWidth(tpe).toInt
Expand Down Expand Up @@ -108,20 +108,20 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
case (None, Some(re)) => or(portToExpression(re), wmode)
case (None, None) => one
}
val wmask = memPortField(mem, s"RW_$i", "wmask")
val wdata = memPortField(mem, s"RW_$i", "wdata")
val rdata = memPortField(mem, s"RW_$i", "rdata")
val wmask = memPortField(mem, s"RW$i", "wmask")
val wdata = memPortField(mem, s"RW$i", "wdata")
val rdata = memPortField(mem, s"RW$i", "rdata")
val write = portToExpression(rw.src.input.get)
val read = (dataType: @unchecked) match {
case VectorType(tpe, size) => cat(((0 until size) map (k =>
WSubIndex(rdata, k, tpe, UNKNOWNGENDER))).reverse)
case _: UIntType => rdata
}
Seq(
Connect(NoInfo, memPortField(mem, s"RW_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"RW_$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"RW_$i", "en"), enable),
Connect(NoInfo, memPortField(mem, s"RW_$i", "wmode"), wmode),
Connect(NoInfo, memPortField(mem, s"RW$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"RW$i", "addr"), address),
Connect(NoInfo, memPortField(mem, s"RW$i", "en"), enable),
Connect(NoInfo, memPortField(mem, s"RW$i", "wmode"), wmode),
Connect(NoInfo, WRef(rw.src.output.get.name), read)
) ++ (dataType match {
case VectorType(tpe, size) =>
Expand Down