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ADD: bump
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@T-K-233
T-K-233 committed Dec 17, 2024
1 parent c83a9d7 commit 606fbd5
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Showing 5 changed files with 188 additions and 127 deletions.
25 changes: 23 additions & 2 deletions src/main/scala/Elaborate.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,7 @@ object GenerateBitstream extends App {
// create Vivado IPs
run_tcl.println("update_ip_catalog")

{
val ip_name = "clk_wiz_0"

run_tcl.println(s"create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name ${ip_name}")
Expand All @@ -144,7 +145,7 @@ object GenerateBitstream extends App {
set_property -dict [list \
CONFIG.CLKOUT1_JITTER {125.247} \
CONFIG.CLKOUT1_PHASE_ERROR {98.575} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \
CONFIG.CLKOUT2_JITTER {175.402} \
CONFIG.CLKOUT2_PHASE_ERROR {98.575} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {25} \
Expand All @@ -153,13 +154,33 @@ object GenerateBitstream extends App {
CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {40} \
CONFIG.NUM_OUT_CLKS {2} \
] [get_ips clk_wiz_0]""")
] [get_ips ${ip_name}]""")


run_tcl.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
run_tcl.println(s"generate_target all [get_ips ${ip_name}]")
run_tcl.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
run_tcl.println(s"create_ip_run [get_ips ${ip_name}]")
}

{
val ip_name = "axis_data_fifo_0"

run_tcl.println(s"create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name ${ip_name}")

run_tcl.println("""
set_property -dict [list \
CONFIG.HAS_TLAST {1} \
CONFIG.TUSER_WIDTH {1 } \
] [get_ips axis_data_fifo_0]
""")

run_tcl.println(s"generate_target {instantiation_template} [get_ips ${ip_name}]")
run_tcl.println(s"generate_target all [get_ips ${ip_name}]")
run_tcl.println(s"export_ip_user_files -of_objects [get_ips ${ip_name}] -no_script -sync -force -quiet")
run_tcl.println(s"create_ip_run [get_ips ${ip_name}]")

}

run_tcl.close()
run_tcl.flush() // make sure the file is written to the disk
Expand Down
137 changes: 72 additions & 65 deletions src/main/scala/TinyRocketArty100T.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ class TinyRocketArty100T extends Arty100TShell {
val pll_locked = Wire(Bool())
val cbus_reset = Wire(Bool())
val jtag_reset = Wire(Bool())

val clock_25 = Wire(Clock())


Expand All @@ -35,90 +36,96 @@ class TinyRocketArty100T extends Arty100TShell {
jtag_reset := debug_sync_reset.io.out


// val digital_top = Module(new DigitalTop)
val digital_top = Module(new DigitalTop)
val udp_core = Module(new udp_core)


withClockAndReset(clock, reset) {
// digital_top.io.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock := clock
// digital_top.io.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset := reset

// cbus_reset := digital_top.io.auto_cbus_fixedClockNode_anon_out_reset
// digital_top.io.resetctrl_hartIsInReset_0 := cbus_reset
digital_top.io.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock := clock
digital_top.io.auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset := reset

// digital_top.io.debug_clock := clock
// digital_top.io.debug_reset := reset
cbus_reset := digital_top.io.auto_cbus_fixedClockNode_anon_out_reset
digital_top.io.resetctrl_hartIsInReset_0 := cbus_reset

// digital_top.io.debug_systemjtag.jtag.TCK := io.jd_2
// digital_top.io.debug_systemjtag.jtag.TMS := io.jd_5
// digital_top.io.debug_systemjtag.jtag.TDI := io.jd_4
// io.jd_0 := digital_top.io.debug_systemjtag.jtag.TDO.data
// digital_top.io.debug_systemjtag.reset := jtag_reset
digital_top.io.debug_clock := clock
digital_top.io.debug_reset := reset

// digital_top.io.debug_dmactiveAck := true.B
digital_top.io.debug_systemjtag.jtag.TCK := io.jd_2
digital_top.io.debug_systemjtag.jtag.TMS := io.jd_5
digital_top.io.debug_systemjtag.jtag.TDI := io.jd_4
io.jd_0 := digital_top.io.debug_systemjtag.jtag.TDO.data
digital_top.io.debug_systemjtag.reset := jtag_reset

// digital_top.io.custom_boot := true.B
digital_top.io.debug_dmactiveAck := true.B

// digital_top.io.serial_tl_0.in.valid := false.B
// digital_top.io.serial_tl_0.in.bits.phit := 0.U(32.W)
// digital_top.io.serial_tl_0.out.ready := true.B
// digital_top.io.serial_tl_0.clock_in := clock

// digital_top.io.uart_0_rxd := false.B
// // io.uart_rxd_out := digital_top.io.uart_0_txd

cbus_reset := false.B
io.jd_0 := false.B
digital_top.io.custom_boot := true.B

digital_top.io.serial_tl_0.in.valid := false.B
digital_top.io.serial_tl_0.in.bits.phit := 0.U(32.W)
digital_top.io.serial_tl_0.out.ready := true.B
digital_top.io.serial_tl_0.clock_in := clock

digital_top.io.uart_0_rxd := false.B
// io.uart_rxd_out := digital_top.io.uart_0_txd

udp_core.io.clk := clock
udp_core.io.rst := reset

udp_core.io.btn := io.btn
udp_core.io.sw := io.sw

io.led0.r := udp_core.io.led0_r
io.led0.g := udp_core.io.led0_g
io.led0.b := udp_core.io.led0_b

io.led1.r := udp_core.io.led1_r
io.led1.g := udp_core.io.led1_g
io.led1.b := udp_core.io.led1_b
udp_core.io.clk := clock
udp_core.io.rst := reset

io.led2.r := udp_core.io.led2_r
io.led2.g := udp_core.io.led2_g
io.led2.b := udp_core.io.led2_b
udp_core.io.btn := io.btn
udp_core.io.sw := io.sw

io.led3.r := udp_core.io.led3_r
io.led3.g := udp_core.io.led3_g
io.led3.b := udp_core.io.led3_b
io.led0.r := udp_core.io.led0_r
io.led0.g := udp_core.io.led0_g
io.led0.b := udp_core.io.led0_b

io.led := Cat(udp_core.io.led7, udp_core.io.led6, udp_core.io.led5, udp_core.io.led4)
io.jd_3 := false.B
io.led1.r := udp_core.io.led1_r
io.led1.g := udp_core.io.led1_g
io.led1.b := udp_core.io.led1_b

io.uart_rxd_out := udp_core.io.uart_txd
udp_core.io.uart_rxd := io.uart_txd_in
io.led2.r := udp_core.io.led2_r
io.led2.g := udp_core.io.led2_g
io.led2.b := udp_core.io.led2_b

io.eth_ref_clk := clock_25
udp_core.io.phy_col := io.eth_col
udp_core.io.phy_crs := io.eth_crs
io.eth_rstn := udp_core.io.phy_reset_n
udp_core.io.phy_rx_clk := io.eth_rx_clk
udp_core.io.phy_rx_dv := io.eth_rx_dv
udp_core.io.phy_rxd := io.eth_rxd
udp_core.io.phy_rx_er := io.eth_rxerr
udp_core.io.phy_tx_clk := io.eth_tx_clk
io.eth_tx_en := udp_core.io.phy_tx_en
io.eth_txd := udp_core.io.phy_txd
io.led3.r := udp_core.io.led3_r
io.led3.g := udp_core.io.led3_g
io.led3.b := udp_core.io.led3_b

io.led := Cat(udp_core.io.led7, udp_core.io.led6, udp_core.io.led5, udp_core.io.led4)

io.jd_3 := false.B

io.uart_rxd_out := udp_core.io.uart_txd
udp_core.io.uart_rxd := io.uart_txd_in

io.eth_ref_clk := clock_25
udp_core.io.phy_col := io.eth_col
udp_core.io.phy_crs := io.eth_crs
io.eth_rstn := udp_core.io.phy_reset_n
udp_core.io.phy_rx_clk := io.eth_rx_clk
udp_core.io.phy_rx_dv := io.eth_rx_dv
udp_core.io.phy_rxd := io.eth_rxd
udp_core.io.phy_rx_er := io.eth_rxerr
udp_core.io.phy_tx_clk := io.eth_tx_clk
io.eth_tx_en := udp_core.io.phy_tx_en
io.eth_txd := udp_core.io.phy_txd


val udp_payload_axis_fifo = Module(new axis_data_fifo_0(8))
udp_payload_axis_fifo.io.s_axis_aresetn := ~reset
udp_payload_axis_fifo.io.s_axis_aclk := clock

udp_payload_axis_fifo.io.s_axis_tvalid := udp_core.io.rx_fifo_udp_payload_axis_tvalid
udp_core.io.rx_fifo_udp_payload_axis_tready := udp_payload_axis_fifo.io.s_axis_tready
udp_payload_axis_fifo.io.s_axis_tdata := udp_core.io.rx_fifo_udp_payload_axis_tdata
udp_payload_axis_fifo.io.s_axis_tlast := udp_core.io.rx_fifo_udp_payload_axis_tlast
udp_payload_axis_fifo.io.s_axis_tuser := udp_core.io.rx_fifo_udp_payload_axis_tuser

udp_core.io.tx_fifo_udp_payload_axis_tvalid := udp_payload_axis_fifo.io.m_axis_tvalid
udp_payload_axis_fifo.io.m_axis_tready := udp_core.io.tx_fifo_udp_payload_axis_tready
udp_core.io.tx_fifo_udp_payload_axis_tdata := udp_payload_axis_fifo.io.m_axis_tdata
udp_core.io.tx_fifo_udp_payload_axis_tlast := udp_payload_axis_fifo.io.m_axis_tlast
udp_core.io.tx_fifo_udp_payload_axis_tuser := udp_payload_axis_fifo.io.m_axis_tuser

// udp_core.io.tx_fifo_udp_payload_axis_tdata := udp_core.io.rx_fifo_udp_payload_axis_tdata
// udp_core.io.tx_fifo_udp_payload_axis_tvalid := udp_core.io.rx_fifo_udp_payload_axis_tvalid
// udp_core.io.rx_fifo_udp_payload_axis_tready := udp_core.io.tx_fifo_udp_payload_axis_tready
// udp_core.io.tx_fifo_udp_payload_axis_tlast := udp_core.io.rx_fifo_udp_payload_axis_tlast
// udp_core.io.tx_fifo_udp_payload_axis_tuser := udp_core.io.rx_fifo_udp_payload_axis_tuser

}
}
20 changes: 20 additions & 0 deletions src/main/scala/wrapper/AXIStreamDataFIFO.scala
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Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@
import chisel3.{BlackBox, _}
import chisel3.util._


class axis_data_fifo_0(width: Int) extends BlackBox {
val io = IO(new Bundle {
val s_axis_aresetn = Input(Reset())
val s_axis_aclk = Input(Clock())
val s_axis_tvalid = Input(Bool())
val s_axis_tready = Output(Bool())
val s_axis_tdata = Input(UInt(width.W))
val s_axis_tlast = Input(Bool())
val s_axis_tuser = Input(Bool())
val m_axis_tvalid = Output(Bool())
val m_axis_tready = Input(Bool())
val m_axis_tdata = Output(UInt(width.W))
val m_axis_tlast = Output(Bool())
val m_axis_tuser = Output(Bool())
})
}
20 changes: 10 additions & 10 deletions src/main/scala/wrapper/UDPCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -40,17 +40,17 @@ class udp_core extends BlackBox {
val uart_rxd = Input(Bool())
val uart_txd = Output(Bool())

// val rx_fifo_udp_payload_axis_tdata = Output(UInt(8.W))
// val rx_fifo_udp_payload_axis_tvalid = Output(Bool())
// val rx_fifo_udp_payload_axis_tready = Input(Bool())
// val rx_fifo_udp_payload_axis_tlast = Output(Bool())
// val rx_fifo_udp_payload_axis_tuser = Output(Bool())
val rx_fifo_udp_payload_axis_tdata = Output(UInt(8.W))
val rx_fifo_udp_payload_axis_tvalid = Output(Bool())
val rx_fifo_udp_payload_axis_tready = Input(Bool())
val rx_fifo_udp_payload_axis_tlast = Output(Bool())
val rx_fifo_udp_payload_axis_tuser = Output(Bool())

// val tx_fifo_udp_payload_axis_tdata = Input(UInt(8.W))
// val tx_fifo_udp_payload_axis_tvalid = Input(Bool())
// val tx_fifo_udp_payload_axis_tready = Output(Bool())
// val tx_fifo_udp_payload_axis_tlast = Input(Bool())
// val tx_fifo_udp_payload_axis_tuser = Input(Bool())
val tx_fifo_udp_payload_axis_tdata = Input(UInt(8.W))
val tx_fifo_udp_payload_axis_tvalid = Input(Bool())
val tx_fifo_udp_payload_axis_tready = Output(Bool())
val tx_fifo_udp_payload_axis_tlast = Input(Bool())
val tx_fifo_udp_payload_axis_tuser = Input(Bool())
})
}

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