riscv targets: add is_cross, is_bare & cross_compiler properties

mlonmcu/target/riscv/riscv.py

@@ -287,6 +287,25 @@ def fpu(self):
     def has_fpu(self):
         return self.fpu != "none"
 
+    @property
+    def is_cross(self):
+        return True
+
+    @property
+    def is_bare(self):
+        if "elf" in self.riscv_gcc_prefix:
+            return True
+        elif "linux" in self.riscv_gcc_prefix:
+            return False
+        else:
+            return None  # unknown
+
+    @property
+    def cross_compiler(self):
+        if not self.is_cross:
+            return None
+        return f"{self.riscv_gcc_basename}-g++"
+
     @property
     def toolchain(self):
         value = self.config.get("mlif.toolchain", None)
@@ -311,6 +330,7 @@ def get_platform_defs(self, platform):
         ret["RISCV_MCPU"] = self.cpu
         # llvm/clang only!
         ret["RISCV_ATTR"] = self.attr
+        ret["RISCV_LINUX"] = not self.is_bare  # TODO: add -static if linux gcc is used
 
         def feature_helper(attrs):
             # TODO
@@ -336,6 +356,7 @@ def get_backend_config(self, backend, optimized_layouts=False, optimized_schedul
                     "target_model": f"etiss-{arch_clean}",
                     # "target_model": f"{self.name}-{arch_clean}",
                     "target_num_cores": 1,  # TODO: also add for non-riscv targets
+                    "cross_compiler": self.cross_compiler,
                     # "target_device": ?,
                     # "target_libs": ?,
                     # "target_tag": ?,