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mlonmcu/target/riscv/riscv.py: add zifencei to gcc arch
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PhilippvK committed Nov 21, 2024
1 parent e13c307 commit 07a9fb4
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion mlonmcu/target/riscv/riscv.py
Original file line number Diff line number Diff line change
Expand Up @@ -209,7 +209,7 @@ def extensions(self):
@property
def gcc_extensions(self):
# return [ext for ext in (self.extensions | {"zicsr"}) if ext not in ["xcorev", "xcorevmac", "xcorevmem"]]
exts = {"zicsr"}
exts = {"zicsr", "zifencei"}
for ext in self.extensions:
if "xcv" in ext:
if ext[-2] != "p":
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