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Fix merge error and compile error and bugs in buildInitValue #13

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May 30, 2024
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3 changes: 2 additions & 1 deletion third_party/cpu/include/TritonToTritonCPU/Passes.td
Original file line number Diff line number Diff line change
Expand Up @@ -83,7 +83,8 @@ def ConvertHistogramOp : Pass<"triton-cpu-convert-histogram-op", "mlir::ModuleOp

let dependentDialects = ["mlir::arith::ArithDialect",
"mlir::memref::MemRefDialect",
"mlir::vector::VectorDialect",
"mlir::vector::VectorDialect"];
}

def ConvertReductionOp : Pass<"triton-cpu-convert-reduction", "mlir::ModuleOp"> {
let summary = "Convert Triton ReduceOp.";
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Original file line number Diff line number Diff line change
Expand Up @@ -149,11 +149,11 @@ struct ReduceOpConversion : public OpConversionPattern<triton::ReduceOp> {
else if (kind == vector::CombiningKind::MAXSI)
initVal = rewriter.getIntegerAttr(
elemTy,
static_cast<int64_t>(1UL << (elemTy.getIntOrFloatBitWidth() - 1)));
static_cast<int64_t>(-(1UL << (elemTy.getIntOrFloatBitWidth() - 1))));
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This would be a sort of INT_MIN. But super interestingly, the dump of initVal remained the same? But what do you think? I think this explicit - is clearer for signed int64_t?

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Is the point here to always have negative int64_t passed to the attribute? The dump is similar because with your change you modify only those bits that don't matter for the used type.

else if (kind == vector::CombiningKind::MINSI)
initVal = rewriter.getIntegerAttr(
elemTy, static_cast<int64_t>(
1UL << (elemTy.getIntOrFloatBitWidth() - 1) - 1));
(1UL << (elemTy.getIntOrFloatBitWidth() - 1)) - 1));
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Clang compiler complains this:

Operator '<<' has lower precedence than '-'; '-' will be evaluated first (fix available)clang(-Wshift-op-parentheses)

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Thanks for the fix. Do you think we also need to change 1UL to 1ULL or use an explicit cast to uint64_t to have all compilers covered?

else if (kind == vector::CombiningKind::MINIMUMF ||
kind == vector::CombiningKind::MINNUMF) {
if (elemTy.isF32())
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