Vitis In-Depth Tutorials
This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.
Error detection enabled tau-NAF conversion on Koblitz Curves
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
example of using iio to stream data from AD9361 with a coax cable loopback
CyDAQ DSP Platform Firmware and Software Redesign - Iowa State University Senior Design May 2023 Group 47 - Blake Fisher, Cole Langner, Corbin Kems, Jens Rasmussen, Long Zeng, Wyatt Duberstein, Yohan Bopearatchy
A TFTP server running on Zynq-7000
Clone of AMD / Xilinx XRT repo from https://github.com/Xilinx/XRT. Major patches and builds / works on Fedora 39.
Example workflow project for firmware development in Vitis.
Baremetal C application that displays encoder values on a serial interface, starting from a Vivado block design and transitioning to a Vitis application.
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