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Matrix multiplication on multiple Nios II cores
POSIX-compatible tiny multi-threading library for Intel Nios II / Xilinx Zynq-7000
Connect a modern, high-resolution camera to an FPGA and easily develop your applications
Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.
Hardware Description Languages
SHA-1 implementation on Nios II soft-core processor with C and SystemVerilog.
Code from FPGA programming with the Altera Nios II
Garfield (ALF 2.0)@ OTH Regensburg, seeing @
C applications for NIOS soc
Frogger-inspired game, set in the Toronto area. Built for Terasic's DE1-SoC platform.
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