Add 128-bit atomic instructions table from issue comment

From #10 (comment).

README.md

@@ -46,7 +46,7 @@ On x86_64, even if `cmpxchg16b` is not available at compile time (note: `cmpxchg
 
 They are usually implemented using inline assembly, and when using Miri or ThreadSanitizer that do not support inline assembly, core intrinsics are used instead of inline assembly if possible.
 
-See [this list](https://github.com/taiki-e/portable-atomic/issues/10#issuecomment-1159368067) for details.
+See also [the `atomic128` module's readme](https://github.com/taiki-e/portable-atomic/blob/HEAD/src/imp/atomic128/README.md).
 
 ## Optional features
 
@@ -87,7 +87,7 @@ See [this list](https://github.com/taiki-e/portable-atomic/issues/10#issuecommen
   additionally on MSP430 `add`, `sub`, `and`, `or`, `xor`, `not`). Therefore, for better performance, if
   all the `critical-section` implementation for your target does is disable interrupts, prefer using
   `--cfg portable_atomic_unsafe_assume_single_core` instead.
-  
+
   Note:
   - The MSRV when this feature enables depends on the MSRV of [critical-section].
 
@@ -131,7 +131,7 @@ See [this list](https://github.com/taiki-e/portable-atomic/issues/10#issuecommen
   - This is compatible with no-std (as with all features except `std`).
   - Some aarch64 targets enable LLVM's `outline-atomics` target feature by default, so if you set this cfg, you may want to disable that as well.
 
-  See also [this list](https://github.com/taiki-e/portable-atomic/issues/10#issuecomment-1159368067).
+  See also [the `atomic128` module's readme](https://github.com/taiki-e/portable-atomic/blob/HEAD/src/imp/atomic128/README.md).
 
 ## Related Projects
 

src/imp/atomic128/README.md

@@ -0,0 +1,12 @@
+# Implementation of 128-bit atomics
+
+The table of targets that support 128-bit atomics and the instructions used:
+
+| target_arch | load | store | CAS | note |
+| ----------- | ----- | ----- | ---- | ---- |
+| x86_64 | cmpxchg16b or vmovdqa | cmpxchg16b or vmovdqa | cmpxchg16b | cmpxchg16b target feature required. vmovdqa requires Intel or AMD CPU with AVX. <br> Both compile-time and run-time detection are supported for cmpxchg16b. vmovdqa is currently run-time detection only.  <br> Requires rustc 1.59+ when cmpxchg16b target feature is enabled at compile-time, otherwise requires nightly |
+| aarch64 | ldxp/stxp or ldp | ldxp/stxp or stp | ldxp/stxp or casp | casp requires lse target feature, ldp/stp requires lse2 target feature. <br> Both compile-time and run-time detection are supported for lse. lse2 is currently compile-time detection only.  <br> Requires rustc 1.59+ |
+| powerpc64 | lq | stq | lqarx/stqcx. | Little endian or target CPU pwr8+. <br> Requires nightly |
+| s390x | lpq | stpq | cdsg | Requires nightly |
+
+Run-time detections are enabled by default and can be disabled with `--cfg portable_atomic_no_outline_atomics`.