⚠️ Remove UART sim-mode's 32-bit dump

CHANGELOG.md

@@ -33,6 +33,7 @@ mimpid = 0x01080200 => Version 01.08.02.00 => v1.8.2
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 18.07.2023 | 1.8.6.6 | :warning: remove 32-bit data dump mode from UART0/1 sim-mode; [#650](https://github.com/stnolting/neorv32/pull/650) |
 | 16.07.2023 | 1.8.6.5 | :warning: **rework SoC bus system & memory map - part 3**: re-enforce PMAs (physical memory attributes); [#648](https://github.com/stnolting/neorv32/pull/648) |
 | 15.07.2023 | 1.8.6.4 | :warning: **rework SoC bus system & memory map - part 2**: move IO address decoding to central IO switch; add i-cache uncached accesses; [#648](https://github.com/stnolting/neorv32/pull/648) |
 | 14.07.2023 | 1.8.6.3 | :warning: **rework SoC bus system & memory map - part 1**: add central bus gateway to control core accesses to the main address regions; [#648](https://github.com/stnolting/neorv32/pull/648) |

docs/datasheet/soc_uart.adoc

@@ -53,7 +53,7 @@ _**Baud rate**_ = (_f~main~[Hz]_ / `clock_prescaler`) / (`baud_div` + 1)
 The control register's `UART_CTRL_RX_*` and `UART_CTRL_TX_*` flags provide information about the RX and TX FIFO fill level.
 Disabling the module via the `UART_CTRL_EN` bit will also clear these FIFOs.
 
-A new TX transmission is started by writing data to the lowest byte of the `DATA` register. The
+A new TX transmission is started by writing to the `DATA` register. The
 transfer is completed when the `UART_CTRL_TX_BUSY` control register flag returns to zero. RX data is available when
 the `UART_CTRL_RX_NEMPTY` flag becomes set. The `UART_CTRL_RX_OVER` will be set if the RX FIFO overflows. This flag
 is cleared by reading the `DATA` register or by disabling the module.
@@ -106,11 +106,8 @@ unconnected. If the CTS handshake is not required it has to be tied to zero.
 
 The UART provides a _simulation-only_ mode to dump console data as well as raw data directly to a file. When the simulation
 mode is enabled (by setting the `UART_CTRL_SIM_MODE` bit) there will be **no** physical transaction on the `uart0_txd_o` signal.
-Instead, all data written to the `DATA` register is immediately dumped to a file.
-
-. Data written to `DATA[7:0]` will be dumped as ASCII chars to a file named `neorv32.uart0.sim_mode.text.out`. Additionally,
-the ASCII data is printed to the simulator console.
-. Data written to `DATA[31:0]` will be dumped as 8-chars ASCII hexadecimal value to a file named `neorv32.uart0.sim_mode.data.out`.
+Instead, all data written to the `DATA` register is immediately dumped to a file. Data written to `DATA[7:0]` will be dumped as
+ASCII chars to a file named `neorv32.uart0.sim_mode.text.out`. Additionally, the ASCII data is printed to the simulator console.
 
 Both file are created in the simulation's home folder.
 
@@ -141,11 +138,10 @@ Both file are created in the simulation's home folder.
                                   <|`29:27` -                                   ^| r/- <| _reserved_ read as zero
                                   <|`30`    `UART_CTRL_RX_OVER`                 ^| r/- <| RX FIFO overflow
                                   <|`31`    `UART_CTRL_TX_BUSY`                 ^| r/- <| TX busy or TX FIFO not empty
-.5+<| `0xfffff504` .3+<| `DATA` <|`7:0`   `UART_DATA_RTX_MSB : UART_DATA_RTX_LSB`                   ^| r/w <| receive/transmit data
+.4+<| `0xfffff504` .4+<| `DATA` <|`7:0`   `UART_DATA_RTX_MSB : UART_DATA_RTX_LSB`                   ^| r/w <| receive/transmit data
                                 <|`11:8`  `UART_DATA_RX_FIFO_SIZE_MSB : UART_DATA_RX_FIFO_SIZE_LSB` ^| r/- <| log2(RX FIFO size)
                                 <|`15:12` `UART_DATA_TX_FIFO_SIZE_MSB : UART_DATA_TX_FIFO_SIZE_LSB` ^| r/- <| log2(RX FIFO size)
                                 <|`31:16` ^| r/- <| _reserved_, read as zero
-                                <|`31:0`  ^| -/w <| **simulation data output**
 |=======================
 
 
@@ -184,9 +180,7 @@ as for the primary UART. The RX and TX interrupts of UART1 are mapped to differe
 **Simulation Mode**
 
 The secondary UART (UART1) provides the same simulation options as the primary UART (UART0). However, output data is
-written to UART1-specific files: `neorv32.uart1.sim_mode.text.out` is used to dump plain ASCII text. This data is also
-printed to the simulator console. `neorv32.uart1.sim_mode.data.out` is used to dump full 32-bit hexadecimal ASCII-chars
-data words.
+written to UART1-specific file `neorv32.uart1.sim_mode.text.out`. This data is also printed to the simulator console.
 
 
 **Register Map**

docs/userguide/simulating_the_processor.adoc

@@ -88,15 +88,14 @@ see section <<_faster_simulation_console_output>>.
 :sectnums:
 === Faster Simulation Console Output
 
-When printing data via the UART the communication speed will always be based on the configured BAUD
+When printing data via the physical UART the communication speed will always be based on the configured BAUD
 rate. For a simulation this might take some time. To have faster output you can enable the **simulation mode**
 for UART0/UART1 (see section https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0[Documentation: Primary Universal Asynchronous Receiver and Transmitter (UART0)]).
 
 ASCII data sent to UART0|UART1 will be immediately printed to the simulator console and logged to files in the simulator
 execution directory:
 
 * `neorv32.uart?.sim_mode.text.out`: ASCII data.
-* `neorv32.uart?.sim_mode.data.out`: all written 32-bit dumped as 8-char hexadecimal values.
 
 You can "automatically" enable the simulation mode of UART0/UART1 when compiling an application.
 In this case, the "real" UART0/UART1 transmitter unit is permanently disabled.

rtl/core/neorv32_package.vhd

@@ -56,7 +56,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080605"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080606"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width, do not change!
 

rtl/core/neorv32_top.vhd

@@ -1100,7 +1100,7 @@ begin
     if (IO_UART0_EN = true) generate
       neorv32_uart0_inst: entity neorv32.neorv32_uart
       generic map (
-        UART_PRIMARY => true,
+        SIM_LOG_FILE => "neorv32.uart0.sim_mode.text.out",
         UART_RX_FIFO => IO_UART0_RX_FIFO,
         UART_TX_FIFO => IO_UART0_TX_FIFO
       )
@@ -1137,7 +1137,7 @@ begin
     if (IO_UART1_EN = true) generate
       neorv32_uart1_inst: entity neorv32.neorv32_uart
       generic map (
-        UART_PRIMARY => false,
+        SIM_LOG_FILE => "neorv32.uart1.sim_mode.text.out",
         UART_RX_FIFO => IO_UART1_RX_FIFO,
         UART_TX_FIFO => IO_UART1_TX_FIFO
       )

rtl/core/neorv32_uart.vhd

@@ -1,5 +1,5 @@
 -- #################################################################################################
--- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART0/1) >>                     #
+-- # << NEORV32 - Universal Asynchronous Receiver and Transmitter (UART) >>                        #
 -- # ********************************************************************************************* #
 -- # Frame configuration: 1 start bit, 8 bit data, parity bit (none/even/odd), 1 stop bit,         #
 -- # programmable BAUD rate via clock pre-scaler and 12-bit BAUD value configuration register,     #
@@ -11,19 +11,11 @@
 -- # * uart_rts_o = 0: RX is ready to receive a new char, enabled via CTRL.ctrl_rts_en_c           #
 -- # * uart_cts_i = 0: TX is allowed to send a new char, enabled via CTRL.ctrl_cts_en_c            #
 -- #                                                                                               #
--- # UART0 / UART1:                                                                                #
--- # This module is used for implementing UART0 and UART1. The UART_PRIMARY generic configures the #
--- # interface register addresses and simulation outputs for UART0 (UART_PRIMARY = true) or UART1  #
--- # (UART_PRIMARY = false).                                                                       #
--- #                                                                                               #
 -- # SIMULATION MODE:                                                                              #
 -- # When the simulation mode is enabled (setting the ctrl.ctrl_sim_en_c bit) any write            #
--- # access to the TX register will not trigger any UART activity. Instead, the written data is    #
--- # output to the simulation environment. The lowest 8 bits of the written data are printed as    #
--- # ASCII char to the simulator console.                                                          #
--- # This char is also stored to the file "neorv32.uartX.sim_mode.text.out" (where X = 0 for UART0 #
--- # and X = 1 for UART1). The full 32-bit write data is also stored as 8-digit hexadecimal value  #
--- # to the file "neorv32.uartX.sim_mode.data.out" (where X = 0 for UART0 and X = 1 for UART1).    #
+-- # access to the TX register will not trigger any physical UART activity. Instead, the written   #
+-- # data is output to the simulation environment. The lowest 8 bits of the TX data are printed    #
+-- # as ASCII char to the simulator console. This char is also stored to the file <SIM_LOG_FILE> . #
 -- # No interrupts are triggered when in SIMULATION MODE.                                          #
 -- # ********************************************************************************************* #
 -- # BSD 3-Clause License                                                                          #
@@ -67,7 +59,7 @@ use std.textio.all;
 
 entity neorv32_uart is
   generic (
-    UART_PRIMARY : boolean; -- true = primary UART (UART0), false = secondary UART (UART1)
+    SIM_LOG_FILE : string;  -- name of SM mode's log file
     UART_RX_FIFO : natural; -- RX fifo depth, has to be a power of two, min 1
     UART_TX_FIFO : natural  -- TX fifo depth, has to be a power of two, min 1
   );
@@ -89,13 +81,6 @@ end neorv32_uart;
 
 architecture neorv32_uart_rtl of neorv32_uart is
 
-  -- simulation output configuration --
-  constant sim_screen_output_en_c : boolean := true; -- output lowest byte as char to simulator console when enabled
-  constant sim_text_output_en_c   : boolean := true; -- output lowest byte as char to text file when enabled
-  constant sim_data_output_en_c   : boolean := true; -- dump 32-bit TX word to file when enabled
-  constant sim_uart_text_file_c   : string  := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.text.out", "neorv32.uart1.sim_mode.text.out");
-  constant sim_uart_data_file_c   : string  := cond_sel_string_f(UART_PRIMARY, "neorv32.uart0.sim_mode.data.out", "neorv32.uart1.sim_mode.data.out");
-
   -- control register bits --
   constant ctrl_en_c            : natural :=  0; -- r/w: UART enable
   constant ctrl_sim_en_c        : natural :=  1; -- r/w: simulation-mode enable
@@ -197,9 +182,9 @@ begin
   -- Sanity Checks --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   assert not (is_power_of_two_f(UART_RX_FIFO) = false)
-    report "NEORV32 PROCESSOR CONFIG ERROR: UART" & cond_sel_string_f(UART_PRIMARY, "0", "1") & " FIFO depth has to be a power of two." severity error;
+    report "NEORV32 PROCESSOR CONFIG ERROR: UART RX FIFO depth has to be a power of two." severity error;
   assert not (is_power_of_two_f(UART_TX_FIFO) = false)
-    report "NEORV32 PROCESSOR CONFIG ERROR: UART" & cond_sel_string_f(UART_PRIMARY, "0", "1") & " FIFO depth has to be a power of two." severity error;
+    report "NEORV32 PROCESSOR CONFIG ERROR: UART TX FIFO depth has to be a power of two." severity error;
 
 
   -- Host Access ----------------------------------------------------------------------------
@@ -514,52 +499,30 @@ begin
   -- -------------------------------------------------------------------------------------------
   simulation_transmitter:
   if (is_simulation_c = true) generate -- for SIMULATION ONLY!
-    process(clk_i)
-      file file_uart_text_out : text open write_mode is sim_uart_text_file_c;
-      file file_uart_data_out : text open write_mode is sim_uart_data_file_c;
-      variable char_v         : integer;
-      variable line_screen_v  : line; -- we need several line variables here since "writeline" seems to flush the source variable
-      variable line_text_v    : line;
-      variable line_data_v    : line;
+    sim_tx: process(clk_i)
+      file file_out          : text open write_mode is SIM_LOG_FILE;
+      variable char_v        : integer;
+      variable line_screen_v : line; -- we need several line variables here since "writeline" seems to flush the source variable
+      variable line_file_v   : line;
     begin
       if rising_edge(clk_i) then
-        if (ctrl.enable = '1') and (ctrl.sim_mode = '1') and -- UART simulation mode
-           (bus_req_i.we = '1') and (bus_req_i.addr(2) = '1') then
-
-          -- print lowest byte as ASCII char --
+        if (ctrl.enable = '1') and (ctrl.sim_mode = '1') and (bus_req_i.we = '1') and (bus_req_i.addr(2) = '1') then
+          -- convert lowest byte to ASCII char --
           char_v := to_integer(unsigned(bus_req_i.data(7 downto 0)));
-          if (char_v >= 128) then -- out of range?
+          if (char_v >= 128) then -- out of printable range?
             char_v := 0;
           end if;
-
           -- ASCII output --
           if (char_v /= 10) and (char_v /= 13) then -- skip line breaks - they are issued via "writeline"
-            if (sim_screen_output_en_c = true) then
-              write(line_screen_v, character'val(char_v));
-            end if;
-            if (sim_text_output_en_c = true) then
-              write(line_text_v, character'val(char_v));
-            end if;
+            write(line_screen_v, character'val(char_v)); -- console
+            write(line_file_v, character'val(char_v)); -- log file
           elsif (char_v = 10) then -- line break: write to screen and text file
-            if (sim_screen_output_en_c = true) then
-              writeline(output, line_screen_v);
-            end if;
-            if (sim_text_output_en_c = true) then
-              writeline(file_uart_text_out, line_text_v);
-            end if;
+            writeline(output, line_screen_v); -- console
+            writeline(file_out, line_file_v); -- log file
           end if;
-
-          -- dump raw data as 8 hex chars to file --
-          if (sim_data_output_en_c = true) then
-            for x in 7 downto 0 loop
-              write(line_data_v, to_hexchar_f(bus_req_i.data(3+x*4 downto 0+x*4))); -- write in hex form
-            end loop;
-            writeline(file_uart_data_out, line_data_v);
-          end if;
-
         end if;
       end if;
-    end process;
+    end process sim_tx;
   end generate;
 
 

sim/simple/ghdl.run.sh

@@ -8,12 +8,11 @@ echo "Tip: Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to auto-ena
 
 # Prepare simulation output files for UART0 and UART 1
 # - Testbench receiver log file (neorv32.testbench_uart?.out)
-# - Direct simulation output (neorv32.uart?.sim_mode.[text|data].out)
+# - Direct simulation output (neorv32.uart?.sim_mode.text.out)
 for uart in 0 1; do
   for item in \
     testbench_uart"$uart" \
-    uart"$uart".sim_mode.text \
-    uart"$uart".sim_mode.data; do
+    uart"$uart".sim_mode.text; do
     touch neorv32."$item".out
     chmod 777 neorv32."$item".out
   done