update simulation instruction (new path)

[rafaelcorsi]

No description provided.

[stnolting]

Eagle eyes! 😉
Thank you very much!

However, I think we should modify the whole section of the user guide here. The "non-simple" testbench uses GHDL per default as well. 🤔

[rafaelcorsi]

Eagle eyes! wink
Thank you very much!

However, I think we should modify the whole section of the user guide here. The "non-simple" testbench uses GHDL per default as well. thinking

I dont know what im doing wrong, but i can not simulate with the run.py nor run_riscv_arch_test.sh scripts. I didn't have time to analyze why.

I know this isn't the place to ask this, but have you ever succeeded to simulate with modelsim? I hate gtkwave....

[stnolting]

I dont know what im doing wrong, but i can not simulate with the run.py nor run_riscv_arch_test.sh scripts. I didn't have time to analyze why.

run_riscv_arch_test.sh is intended for running the official RISC-V architecture tests only.

You can simulate the processor using the "simple" tesbench and scripts: neorv32/sim/simple$ sh ghdl.sh

If you want to do a "quick" simulation while compiling an application you can do:

neorv32/sw/example/hello_world$ make USER_FLAGS+=-DUART_SIM_MODE MARCH=-march=rv32imac clean_all sim

• USER_FLAGS+=-DUART_SIM_MODE redirects all UART0 output from the physical transmitter to the simulator console (faster output)
• MARCH=-march=rv32imac enable standard RISC-V ISA extensions for compilation
• the sim target basically calls neorv32/sim/simple/ghdl.sh

I know this isn't the place to ask this, but have you ever succeeded to simulate with modelsim? I hate gtkwave....

Most of the time I am using Xilinx ISIM, but sometimes I am using Modelsim, too. So no problems here. Maybe it is a library issue? If you like you can open a new discussion if you like to discuss this. Sounds like an issue other people might also have problems with.

[umarcor]

This was my bad indeed...

@stnolting, note that VUnit does not use GHDL by default. In CI, GHDL is the only simulator we can use, so that is the only one that VUnit can find. However, locally the same script can be used with ModelSim/QuestaSim, Riviera PRO, etc. Precisely, VUnit allows selecting the simulator through an envvar: http://vunit.github.io/cli.html#simulator-selection

[umarcor]

I know this isn't the place to ask this, but have you ever succeeded to simulate with modelsim? I hate gtkwave....

@rafaelcorsi, theoretically, it should be possible to simulate with GHDL and view the VCD waveform with ModelSim. Alternatively, you can execute VUnit with ModelSim (depending on the license, you might run into limits). See the ref in my previous comment.

[stnolting]

@stnolting, note that VUnit does not use GHDL by default. In CI, GHDL is the only simulator we can use, so that is the only one that VUnit can find.

Right... misunderstanding on my side. Thanks for clearing!

[umarcor]

I did some enhancements to section 'Simulating the Processor' and I created #156, which includes the commit in here, thus superseeding this PR.