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[rtl] minor comment edits
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@stnolting
stnolting committed Nov 24, 2024
1 parent 0fbf767 commit 9401b9a
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Showing 3 changed files with 22 additions and 23 deletions.
31 changes: 15 additions & 16 deletions rtl/core/neorv32_cpu_control.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -408,7 +408,7 @@ begin


-- ****************************************************************************************************************************
-- Instruction Issue (decompress 16-bit instructions and assemble a 32-bit instruction word)
-- Instruction Issue (decompress 16-bit instruction and/or assemble a 32-bit instruction word)
-- ****************************************************************************************************************************

issue_engine_enabled:
Expand Down Expand Up @@ -501,15 +501,14 @@ begin
if (rstn_i = '0') then
alu_imm_o <= (others => '0');
elsif rising_edge(clk_i) then
if (exe_engine.state = DISPATCH) then -- prepare update of next pc (using ALU's PC + IMM in EXECUTE state)
if (exe_engine.state = DISPATCH) then -- prepare update of next PC (using ALU's PC + IMM in EXECUTE state)
alu_imm_o <= (others => '0');
if RISCV_ISA_C and (issue_engine.data(33) = '1') then -- is de-compressed C instruction?
alu_imm_o(3 downto 0) <= x"2";
else
alu_imm_o(3 downto 0) <= x"4";
end if;
else
alu_imm_o <= replicate_f(exe_engine.ir(31), 21) & exe_engine.ir(30 downto 21) & exe_engine.ir(20); -- default: I-immediate
case opcode is
when opcode_store_c => -- S-immediate
alu_imm_o <= replicate_f(exe_engine.ir(31), 21) & exe_engine.ir(30 downto 25) & exe_engine.ir(11 downto 7);
Expand All @@ -520,9 +519,9 @@ begin
when opcode_jal_c => -- J-immediate
alu_imm_o <= replicate_f(exe_engine.ir(31), 12) & exe_engine.ir(19 downto 12) & exe_engine.ir(20) & exe_engine.ir(30 downto 21) & '0';
when opcode_amo_c => -- atomic memory access
if RISCV_ISA_Zalrsc then alu_imm_o <= (others => '0'); end if;
when others =>
NULL; -- use default
alu_imm_o <= (others => '0');
when others => -- I-immediate
alu_imm_o <= replicate_f(exe_engine.ir(31), 21) & exe_engine.ir(30 downto 21) & exe_engine.ir(20);
end case;
end if;
end if;
Expand Down Expand Up @@ -635,21 +634,21 @@ begin

when DISPATCH => -- wait for ISSUE ENGINE to emit a valid instruction word
-- ------------------------------------------------------------
ctrl_nxt.alu_opa_mux <= '1'; -- prepare update of next pc in EXECUTE (opa = current_pc)
ctrl_nxt.alu_opb_mux <= '1'; -- prepare update of next pc in EXECUTE (opb = imm = +2/4)
ctrl_nxt.alu_opa_mux <= '1'; -- prepare update of next PC in EXECUTE (opa = current PC)
ctrl_nxt.alu_opb_mux <= '1'; -- prepare update of next PC in EXECUTE (opb = imm = +2/4)
--
if (trap_ctrl.env_pending = '1') or (trap_ctrl.exc_fire = '1') then -- pending trap or pending exception (fast)
exe_engine_nxt.state <= TRAP_ENTER;
elsif RISCV_ISA_Sdtrig and (hw_trigger_match = '1') then -- hardware breakpoint
exe_engine_nxt.pc <= exe_engine.pc2(XLEN-1 downto 1) & '0'; -- pc <= next pc; intercept BEFORE executing the instruction
exe_engine_nxt.pc <= exe_engine.pc2(XLEN-1 downto 1) & '0'; -- PC <= next PC; intercept BEFORE executing the instruction
trap_ctrl.hwtrig <= '1';
exe_engine_nxt.state <= DISPATCH; -- stay here another round until trap_ctrl.hwtrig arrives in trap_ctrl.env_pending
elsif (issue_engine.valid(0) = '1') or (issue_engine.valid(1) = '1') then -- new instruction word available
issue_engine.ack <= '1';
trap_ctrl.instr_be <= issue_engine.data(32); -- access fault during instruction fetch
exe_engine_nxt.ci <= issue_engine.data(33); -- this is a de-compressed instruction
exe_engine_nxt.ir <= issue_engine.data(31 downto 0); -- instruction word
exe_engine_nxt.pc <= exe_engine.pc2(XLEN-1 downto 1) & '0'; -- pc <= next pc
exe_engine_nxt.pc <= exe_engine.pc2(XLEN-1 downto 1) & '0'; -- PC <= next PC
exe_engine_nxt.state <= EXECUTE; -- start executing new instruction
end if;

Expand All @@ -661,9 +660,9 @@ begin
exe_engine_nxt.pc2 <= DEBUG_EXC_ADDR(XLEN-1 downto 2) & "00"; -- debug mode enter: start at "parking loop" <exception_entry>
else -- normal start of trap
if (csr.mtvec(0) = '1') and (trap_ctrl.cause(6) = '1') then -- vectored mode + interrupt
exe_engine_nxt.pc2 <= csr.mtvec(XLEN-1 downto 7) & trap_ctrl.cause(4 downto 0) & "00"; -- pc = mtvec + 4 * mcause
exe_engine_nxt.pc2 <= csr.mtvec(XLEN-1 downto 7) & trap_ctrl.cause(4 downto 0) & "00"; -- PC = mtvec + 4 * mcause
else
exe_engine_nxt.pc2 <= csr.mtvec(XLEN-1 downto 2) & "00"; -- pc = mtvec
exe_engine_nxt.pc2 <= csr.mtvec(XLEN-1 downto 2) & "00"; -- PC = mtvec
end if;
end if;
--
Expand All @@ -682,7 +681,7 @@ begin
trap_ctrl.env_exit <= '1';
exe_engine_nxt.state <= RESTART; -- restart instruction fetch

when RESTART => -- reset and restart instruction fetch at next pc
when RESTART => -- reset and restart instruction fetch at next PC
-- ------------------------------------------------------------
ctrl_nxt.rf_zero_we <= not bool_to_ulogic_f(REGFILE_HW_RST); -- house keeping: force writing zero to x0 if it's a phys. register
fetch_engine.reset <= '1';
Expand All @@ -691,7 +690,7 @@ begin
when EXECUTE => -- decode and execute instruction (control will be here for exactly 1 cycle in any case)
-- [NOTE] register file is read in this stage; due to the sync read, data will be available in the _next_ state
-- ------------------------------------------------------------
exe_engine_nxt.pc2 <= alu_add_i(XLEN-1 downto 1) & '0';
exe_engine_nxt.pc2 <= alu_add_i(XLEN-1 downto 1) & '0'; -- next PC (= PC + immediate)

-- decode instruction class/type --
case opcode is
Expand Down Expand Up @@ -778,7 +777,7 @@ begin
exe_engine_nxt.state <= DISPATCH;
end if;

when BRANCH => -- update next pc on taken branches and jumps
when BRANCH => -- update next PC on taken branches and jumps
-- ------------------------------------------------------------
exe_engine_nxt.ra <= exe_engine.pc2(XLEN-1 downto 1) & '0'; -- output return address
ctrl_nxt.rf_wb_en <= opcode(2); -- save return address if link operation (won't happen if exception)
Expand Down Expand Up @@ -1195,7 +1194,7 @@ begin
if (trap_ctrl.exc_buf(exc_iaccess_c) = '1') then trap_ctrl.cause <= trap_iaf_c; -- instruction access fault
elsif (trap_ctrl.exc_buf(exc_illegal_c) = '1') then trap_ctrl.cause <= trap_iil_c; -- illegal instruction
elsif (trap_ctrl.exc_buf(exc_ialign_c) = '1') then trap_ctrl.cause <= trap_ima_c; -- instruction address misaligned
elsif (trap_ctrl.exc_buf(exc_ecall_c) = '1') then trap_ctrl.cause <= trap_env_c(6 downto 2) & csr.privilege & csr.privilege; -- environment call (U/M)
elsif (trap_ctrl.exc_buf(exc_ecall_c) = '1') then trap_ctrl.cause <= trap_env_c(6 downto 2) & replicate_f(csr.privilege, 2); -- environment call (U/M)
elsif (trap_ctrl.exc_buf(exc_ebreak_c) = '1') then trap_ctrl.cause <= trap_brk_c; -- environment breakpoint
elsif (trap_ctrl.exc_buf(exc_salign_c) = '1') then trap_ctrl.cause <= trap_sma_c; -- store address misaligned
elsif (trap_ctrl.exc_buf(exc_lalign_c) = '1') then trap_ctrl.cause <= trap_lma_c; -- load address misaligned
Expand Down
1 change: 1 addition & 0 deletions rtl/core/neorv32_cpu_lsu.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,7 @@ begin
end if;
end process mem_addr_reg;

-- address output --
dbus_req_o.addr <= mar; -- bus address
mar_o <= mar; -- for MTVAL CSR

Expand Down
13 changes: 6 additions & 7 deletions rtl/core/neorv32_cpu_pmp.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ architecture neorv32_cpu_pmp_rtl of neorv32_cpu_pmp is
-- auto-configuration --
constant granularity_c : natural := cond_sel_natural_f(boolean(GRANULARITY < 4), 4, 2**index_size_f(GRANULARITY));

-- PMP configuration register bits --
-- configuration register bits --
constant cfg_r_c : natural := 0; -- read permit
constant cfg_w_c : natural := 1; -- write permit
constant cfg_x_c : natural := 2; -- execute permit
Expand All @@ -59,16 +59,16 @@ architecture neorv32_cpu_pmp_rtl of neorv32_cpu_pmp is
constant cfg_rh_c : natural := 6; -- reserved
constant cfg_l_c : natural := 7; -- locked entry

-- PMP modes --
-- operation modes --
constant mode_off_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
constant mode_tor_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
constant mode_na4_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
constant mode_napot_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)

-- PMP helpers --
-- address LSB according to granularity --
constant pmp_lsb_c : natural := index_size_f(granularity_c); -- min = 2

-- PMP CSRs --
-- CSRs --
type csr_cfg_t is array (0 to NUM_REGIONS-1) of std_ulogic_vector(7 downto 0);
type csr_addr_t is array (0 to NUM_REGIONS-1) of std_ulogic_vector(XLEN-1 downto 0);
type csr_cfg_rd_t is array (0 to 15) of std_ulogic_vector(7 downto 0);
Expand All @@ -85,7 +85,7 @@ architecture neorv32_cpu_pmp_rtl of neorv32_cpu_pmp is
signal cfg_rd32 : csr_cfg_rd32_t;
signal addr_rd : csr_addr_rd_t;

-- PMP address extension to 34 bit --
-- extended address (34-bit) --
type xaddr_t is array (0 to NUM_REGIONS-1) of std_ulogic_vector(XLEN+1 downto 0);
signal xaddr : xaddr_t;

Expand Down Expand Up @@ -240,7 +240,7 @@ begin
-- extend region addresses to 34-bit --
xaddr(r) <= csr.addr(r) & "00"; -- mask byte offset


-- naturally-aligned address mask --
nap_mode_enable:
if NAP_EN generate

Expand Down Expand Up @@ -366,7 +366,6 @@ begin
fail_rw(r) <= not region.perm_rw(r) when (region.d_match(r) = '1') else fail_rw(r+1);
end generate;


-- final access check --
access_check: process(rstn_i, clk_i)
begin
Expand Down

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