[bus interface] cleanup signals

remove ".sleep", ".debug" is now handled as in-band signal (valid only during an actual transfer)

docs/datasheet/cpu.adoc

@@ -66,7 +66,7 @@ direction as seen from the CPU.
 [options="header", grid="rows"]
 |=======================
 | Signal | Width/Type | Dir | Description
-4+^| **Global Signals**
+4+^| **Clock and Reset**
 | `clk_i`        | 1           | in  | Global clock line, all registers triggering on rising edge.
 | `rstn_i`       | 1           | in  | Global reset, low-active.
 4+^| **Interrupts (<<_traps_exceptions_and_interrupts>>)**
@@ -75,20 +75,17 @@ direction as seen from the CPU.
 | `mti_i`        | 1           | in  | RISC-V machine timer interrupt.
 | `firq_i`       | 16          | in  | Custom fast interrupt request signals.
 | `dbi_i`        | 1           | in  | Request CPU to halt and enter debug mode (RISC-V <<_on_chip_debugger_ocd>>).
+4+^| **<<_inter_core_communication_icc>> links**
+| `icc_tx_o` | `icc_t`         | out | TX link
+| `icc_rx_i` | `icc_t`         | in  | RX link
 4+^| **Instruction <<_bus_interface>>**
 | `ibus_req_o`   | `bus_req_t` | out | Instruction fetch bus request.
 | `ibus_rsp_i`   | `bus_rsp_t` | in  | Instruction fetch bus response.
 4+^| **Data <<_bus_interface>>**
 | `dbus_req_o`   | `bus_req_t` | out | Data access (load/store) bus request.
 | `dbus_rsp_i`   | `bus_rsp_t` | in  | Data access (load/store) bus response.
 4+^| **<<_inter_core_communication_icc>> TX links**
-| `icc_tx_rdy_o` | 2           | out | Data available for cores `0..1`.
-| `icc_tx_ack_i` | 2           | in  | Read-enable from cores `0..1`.
-| `icc_tx_dat_o` | 2*32        | out | Data for cores `0..1`.
-4+^| **<<_inter_core_communication_icc>> RX links**
-| `icc_rx_rdy_i` | 2           | in  | Data available from cores `0..1`.
-| `icc_rx_ack_o` | 2           | out | Read-enable for cores `0..1`.
-| `icc_rx_dat_i` | 2*32        | in  | Data from cores `0..1`.
+| `mem_sync_i`   | 1           | in  | Read-enable from cores `0..1`.
 |=======================
 
 .Bus Interface Protocol
@@ -424,12 +421,11 @@ always valid when set.
 | `rw`    |     1 | Access direction (`0` = read, `1` = write)
 | `src`   |     1 | Access source (`0` = instruction fetch, `1` = load/store)
 | `priv`  |     1 | Set if privileged (M-mode) access
+| `debug` |     1 | Set if debug mode access
 | `amo`   |     1 | Set if current access is an atomic memory operation (<<_atomic_memory_access>>)
 | `amoop` |     4 | Type of atomic memory operation (<<_atomic_memory_access>>)
 3+^| **Out-Of-Band Signals**
 | `fence` |     1 | Data/instruction fence request; single-shot
-| `sleep` |     1 | Set if ALL upstream devices are in <<_sleep_mode>>
-| `debug` |     1 | Set if the upstream device is in debug-mode
 |=======================
 
 .Bus Interface - Response Bus (`bus_rsp_t`)
@@ -463,7 +459,7 @@ The figure below shows three exemplary bus accesses:
 . A write access to address `B_addr` writing `wdata` (fastest response; `ACK` arrives right in the next cycle).
 . A failing read access to address `C_addr` (slow response; `ERR` arrives after several cycles).
 
-.Three Exemplary Bus Transactions (showing only in-band signals)
+.Three Exemplary Bus Transactions (showing only in-band signals; privileged non-debug non-atomic accesses)
 image::bus_interface.png[700]
 
 .Adding Register Stages

docs/sources/bus_interface.json

@@ -7,8 +7,11 @@
     {name: 'ben',   wave: 'x..|..4.x..|..', data: ['ben']},
     {name: 'stb',   wave: '010|..10.10|..', node: '.a....d..f....'},
     {name: 'rw',    wave: '0..|..1..0.|..', node: '..............'},
-    {name: 'src',   wave: 'x0.|.x0.x..|..'},
+    {name: 'src',   wave: 'x1.|.x1.x..|..'},
     {name: 'priv',  wave: 'x0.|.x0.x..|..'},
+    {name: 'debug', wave: 'x0.|.x0.x..|..'},
+    {name: 'amo',   wave: 'x0.|.x0.x..|..'},
+    {name: 'amoop', wave: 'x0.|.x0.x..|..'},
   ],
   {},
   [

rtl/core/neorv32_package.vhd

@@ -29,7 +29,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110006"; -- hardware version
+  constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01110007"; -- hardware version
   constant archid_c     : natural := 19; -- official RISC-V architecture ID
   constant XLEN         : natural := 32; -- native data path width
 
@@ -123,20 +123,19 @@ package neorv32_package is
     data  : std_ulogic_vector(31 downto 0); -- write data
     ben   : std_ulogic_vector(3 downto 0); -- byte enable
     stb   : std_ulogic; -- request strobe, single-shot
-    rw    : std_ulogic; -- 0=read, 1=write
-    src   : std_ulogic; -- access source (1=instruction fetch, 0=data access)
+    rw    : std_ulogic; -- 0 = read, 1 = write
+    src   : std_ulogic; -- 0 = data access, 1 = instruction fetch
     priv  : std_ulogic; -- set if privileged (machine-mode) access
+    debug : std_ulogic; -- set if debug mode access
     amo   : std_ulogic; -- set if atomic memory operation
     amoop : std_ulogic_vector(3 downto 0); -- type of atomic memory operation
     -- out-of-band signals --
-    fence : std_ulogic; -- set if fence(.i) request by upstream device, single-shot
-    sleep : std_ulogic; -- set if ALL upstream sources are in sleep mode
-    debug : std_ulogic; -- set if upstream device is in debug mode
+    fence : std_ulogic; -- set if fence(.i) operation, single-shot
   end record;
 
   -- bus response --
   type bus_rsp_t is record
-    data : std_ulogic_vector(31 downto 0); -- read data, valid if ack=1
+    data : std_ulogic_vector(31 downto 0); -- read data, valid if ack = 1
     ack  : std_ulogic; -- set if access acknowledge, single-shot
     err  : std_ulogic; -- set if access error, single-shot, has priority over ack
   end record;
@@ -150,11 +149,10 @@ package neorv32_package is
     rw    => '0',
     src   => '0',
     priv  => '0',
+    debug => '0',
     amo   => '0',
     amoop => (others => '0'),
-    fence => '0',
-    sleep => '1',
-    debug => '0'
+    fence => '0'
   );
 
   -- endpoint (response) termination --