[rte] minor console output edits

stnolting · Nov 25, 2023 · 75a2d6a · 75a2d6a
1 parent bfbb0c9
commit 75a2d6a
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Showing 2 changed files with 8 additions and 8 deletions.
diff --git a/docs/datasheet/software_rte.adoc b/docs/datasheet/software_rte.adoc
@@ -160,11 +160,11 @@ cannot be resolved by the default debug trap handlers and will halt the CPU (see
 .RTE Default Trap Handler Output Examples
 [source]
 ----
-<RTE> [M] Illegal instruction @ PC=0x000002d6, MTINST=0x000000FF, MTVAL=0x00000000 </RTE> <1>
-<RTE> [U] Illegal instruction @ PC=0x00000302, MTINST=0x00000000, MTVAL=0x00000000 </RTE> <2>
-<RTE> [U] Load address misaligned @ PC=0x00000440, MTINST=0x01052603, MTVAL=0x80000101 </RTE> <3>
-<RTE> [M] Fast IRQ 0x00000003 @ PC=0x00000820, MTINST=0x00000000, MTVAL=0x00000000 </RTE> <4>
-<RTE> [M] Instruction access fault @ PC=0x90000000, MTINST=0x42078b63, MTVAL=0x00000000 [FATAL EXCEPTION] Halting CPU. </RTE>\n <5>
+<NEORV32-RTE> [M] Illegal instruction @ PC=0x000002d6, MTINST=0x000000FF, MTVAL=0x00000000 </NEORV32-RTE> <1>
+<NEORV32-RTE> [U] Illegal instruction @ PC=0x00000302, MTINST=0x00000000, MTVAL=0x00000000 </NEORV32-RTE> <2>
+<NEORV32-RTE> [U] Load address misaligned @ PC=0x00000440, MTINST=0x01052603, MTVAL=0x80000101 </NEORV32-RTE> <3>
+<NEORV32-RTE> [M] Fast IRQ 0x00000003 @ PC=0x00000820, MTINST=0x00000000, MTVAL=0x00000000 </NEORV32-RTE> <4>
+<NEORV32-RTE> [M] Instruction access fault @ PC=0x90000000, MTINST=0x42078b63, MTVAL=0x00000000 !!FATAL EXCEPTION!! Halting CPU. </NEORV32-RTE>\n <5>
 ----
 <1> Illegal 32-bit instruction `MTINST=0x000000FF` at address `PC=0x000002d6` while the CPU was in machine-mode (`[M]`).
 <2> Illegal 16-bit instruction `MTINST=0x00000000` at address `PC=0x00000302` while the CPU was in user-mode (`[U]`).

diff --git a/sw/lib/source/neorv32_rte.c b/sw/lib/source/neorv32_rte.c
@@ -327,7 +327,7 @@ static void __neorv32_rte_debug_handler(void) {
   }
 
   // intro
-  neorv32_uart0_puts("<RTE> ");
+  neorv32_uart0_puts("<NEORV32-RTE> ");
 
   // privilege level of the CPU when the trap occurred
   if (neorv32_cpu_csr_read(CSR_MSTATUS) & (3 << CSR_MSTATUS_MPP_L)) {
@@ -391,15 +391,15 @@ static void __neorv32_rte_debug_handler(void) {
 
   // halt if fatal exception
   if ((trap_cause == TRAP_CODE_I_ACCESS) || (trap_cause == TRAP_CODE_I_MISALIGNED)) {
-    neorv32_uart0_puts(" [FATAL EXCEPTION!] Halting CPU. </RTE>\n");
+    neorv32_uart0_puts(" !!FATAL EXCEPTION!! Halting CPU. </NEORV32-RTE>\n");
     neorv32_cpu_csr_write(CSR_MIE, 0);
     while(1) {
       asm volatile ("wfi");
     }
   }
 
   // outro
-  neorv32_uart0_puts(" </RTE>\n");
+  neorv32_uart0_puts(" </NEORV32-RTE>\n");
 }