⚠️ [sw] remove XIP module

stnolting · Feb 1, 2025 · 57a5027 · 57a5027
1 parent e2233ce
commit 57a5027
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Showing 8 changed files with 3 additions and 907 deletions.
diff --git a/sw/example/demo_xip/main.c b/sw/example/demo_xip/main.c
diff --git a/sw/example/demo_xip/makefile b/sw/example/demo_xip/makefile
diff --git a/sw/lib/include/neorv32.h b/sw/lib/include/neorv32.h
@@ -24,21 +24,11 @@ extern "C" {
 #include <stdlib.h>
 
 
-/**********************************************************************//**
- * @name Main Address Space Sections
- **************************************************************************/
-/**@{*/
-/** XIP-mapped memory base address */
-#define XIP_MEM_BASE_ADDRESS (0xE0000000U)
-/** peripheral/IO devices memory base address */
-#define IO_BASE_ADDRESS      (0XFFE00000U)
-/**@}*/
-
-
 /**********************************************************************//**
  * @name IO Address Space Map - Peripheral/IO Devices
  **************************************************************************/
 /**@{*/
+#define IO_BASE_ADDRESS      (0XFFE00000U)
 #define NEORV32_BOOTROM_BASE (0xFFE00000U) /**< Bootloader ROM (BOOTROM) */
 //#define NEORV32_???_BASE   (0xFFE10000U) /**< reserved */
 //#define NEORV32_???_BASE   (0xFFE20000U) /**< reserved */
@@ -54,7 +44,7 @@ extern "C" {
 #define NEORV32_SLINK_BASE   (0xFFEC0000U) /**< Stream Link Interface (SLINK) */
 #define NEORV32_DMA_BASE     (0xFFED0000U) /**< Direct Memory Access Controller (DMA) */
 #define NEORV32_CRC_BASE     (0xFFEE0000U) /**< Cyclic Redundancy Check Unit (DMA) */
-#define NEORV32_XIP_BASE     (0xFFEF0000U) /**< Execute In Place Module (XIP) */
+//#define NEORV32_???_BASE   (0xFFEF0000U) /**< reserved */
 #define NEORV32_PWM_BASE     (0xFFF00000U) /**< Pulse Width Modulation Controller (PWM) */
 #define NEORV32_GPTMR_BASE   (0xFFF10000U) /**< General Purpose Timer (GPTMR) */
 #define NEORV32_ONEWIRE_BASE (0xFFF20000U) /**< 1-Wire Interface Controller (ONEWIRE) */
@@ -277,7 +267,6 @@ typedef union {
 #include "neorv32_twi.h"
 #include "neorv32_uart.h"
 #include "neorv32_wdt.h"
-#include "neorv32_xip.h"
 
 
 #ifdef __cplusplus

diff --git a/sw/lib/include/neorv32_sysinfo.h b/sw/lib/include/neorv32_sysinfo.h
@@ -52,8 +52,7 @@ enum NEORV32_SYSINFO_SOC_enum {
   SYSINFO_SOC_DCACHE       =  6, /**< SYSINFO_SOC  (6) (r/-): Processor-internal instruction cache implemented when 1 (via DCACHE_EN generic) */
 
   SYSINFO_SOC_XBUS_CACHE   =  8, /**< SYSINFO_SOC  (8) (r/-): External bus cache implemented when 1 (via XBUS_CACHE_EN generic) */
-  SYSINFO_SOC_XIP          =  9, /**< SYSINFO_SOC  (9) (r/-): Execute in-place module implemented when 1 (via XIP_EN generic) */
-  SYSINFO_SOC_XIP_CACHE    = 10, /**< SYSINFO_SOC (10) (r/-): Execute in-place cache implemented when 1 (via XIP_CACHE_EN generic) */
+
   SYSINFO_SOC_OCD_AUTH     = 11, /**< SYSINFO_SOC (11) (r/-): On-chip debugger authentication implemented when 1 (via OCD_AUTHENTICATION generic) */
   SYSINFO_SOC_IMEM_ROM     = 12, /**< SYSINFO_SOC (12) (r/-): Processor-internal instruction memory implemented as pre-initialized ROM when 1 (via BOOT_MODE_SELECT generic) */
   SYSINFO_SOC_IO_TWD       = 13, /**< SYSINFO_SOC (13) (r/-): Two-wire device implemented when 1 (via IO_TWD_EN generic) */
@@ -89,11 +88,6 @@ enum NEORV32_SYSINFO_SOC_enum {
   SYSINFO_CACHE_DATA_NUM_BLOCKS_0 = 12, /**< SYSINFO_CACHE (12) (r/-): d-cache: log2(Number of cache blocks), bit 0 (via DCACHE_NUM_BLOCKS generic) */
   SYSINFO_CACHE_DATA_NUM_BLOCKS_3 = 15, /**< SYSINFO_CACHE (15) (r/-): d-cache: log2(Number of cache blocks), bit 3 (via DCACHE_NUM_BLOCKS generic) */
 
-  SYSINFO_CACHE_XIP_BLOCK_SIZE_0  = 16, /**< SYSINFO_CACHE (16) (r/-): xip-cache: log2(Block size in bytes), bit 0 (via XIP_CACHE_BLOCK_SIZE generic) */
-  SYSINFO_CACHE_XIP_BLOCK_SIZE_3  = 19, /**< SYSINFO_CACHE (19) (r/-): xip-cache: log2(Block size in bytes), bit 3 (via XIP_CACHE_BLOCK_SIZE generic) */
-  SYSINFO_CACHE_XIP_NUM_BLOCKS_0  = 20, /**< SYSINFO_CACHE (20) (r/-): xip-cache: log2(Number of cache blocks), bit 0 (via XIP_CACHE_NUM_BLOCKS generic) */
-  SYSINFO_CACHE_XIP_NUM_BLOCKS_3  = 23, /**< SYSINFO_CACHE (23) (r/-): xip-cache: log2(Number of cache blocks), bit 3 (via XIP_CACHE_NUM_BLOCKS generic) */
-
   SYSINFO_CACHE_XBUS_BLOCK_SIZE_0 = 24, /**< SYSINFO_CACHE (24) (r/-): xbus-cache: log2(Block size in bytes), bit 0 (via XBUS_CACHE_BLOCK_SIZE generic) */
   SYSINFO_CACHE_XBUS_BLOCK_SIZE_3 = 27, /**< SYSINFO_CACHE (27) (r/-): xbus-cache: log2(Block size in bytes), bit 3 (via XBUS_CACHE_BLOCK_SIZE generic) */
   SYSINFO_CACHE_XBUS_NUM_BLOCKS_0 = 28, /**< SYSINFO_CACHE (28) (r/-): xbus-cache: log2(Number of cache blocks), bit 0 (via XBUS_CACHE_NUM_BLOCKS generic) */

diff --git a/sw/lib/include/neorv32_xip.h b/sw/lib/include/neorv32_xip.h
diff --git a/sw/lib/source/neorv32_aux.c b/sw/lib/source/neorv32_aux.c
@@ -459,22 +459,6 @@ void neorv32_aux_print_hw_config(void) {
     neorv32_uart0_printf("none\n");
   }
 
-  // XIP-cache
-  neorv32_uart0_printf("XIP-cache:           ");
-  if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_XIP_CACHE)) {
-
-    uint32_t xip_block_size = (NEORV32_SYSINFO->CACHE >> SYSINFO_CACHE_XIP_BLOCK_SIZE_0) & 0x0F;
-    xip_block_size = 1 << xip_block_size;
-
-    uint32_t xip_num_blocks = (NEORV32_SYSINFO->CACHE >> SYSINFO_CACHE_XIP_NUM_BLOCKS_0) & 0x0F;
-    xip_num_blocks = 1 << xip_num_blocks;
-
-    neorv32_uart0_printf("%u bytes (%ux%u)\n", xip_num_blocks*xip_block_size, xip_num_blocks, xip_block_size);
-  }
-  else {
-    neorv32_uart0_printf("none\n");
-  }
-
   // XBUS-cache
   neorv32_uart0_printf("XBUS-cache:          ");
   if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_XBUS_CACHE)) {
@@ -529,7 +513,6 @@ void neorv32_aux_print_hw_config(void) {
   if (tmp & (1 << SYSINFO_SOC_IO_UART0))   { neorv32_uart0_printf("UART0 ");   }
   if (tmp & (1 << SYSINFO_SOC_IO_UART1))   { neorv32_uart0_printf("UART1 ");   }
   if (tmp & (1 << SYSINFO_SOC_IO_WDT))     { neorv32_uart0_printf("WDT ");     }
-  if (tmp & (1 << SYSINFO_SOC_XIP))        { neorv32_uart0_printf("XIP ");     }
 
   neorv32_uart0_printf("\n\n");
 }