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[Dependabot]: Bump neorv32 from 03ac28b to 651732d #135

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merged 2 commits into from
Jan 4, 2025
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[Dependabot]: Bump neorv32 from 03ac28b to 651732d #135

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[Dependabot]: Bump neorv32 from `03ac28b` to `651732d`
dependabot[bot] Jan 4, 2025
e58986a
[src] update core generics
stnolting Jan 4, 2025
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2 changes: 1 addition & 1 deletion neorv32
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Submodule neorv32 updated 61 files
+2 −0 CHANGELOG.md
+1 −1 LICENSE
+2 −2 README.md
+6 −0 docs/datasheet/content.adoc
+38 −50 docs/datasheet/cpu.adoc
+12 −11 docs/datasheet/cpu_csr.adoc
+82 −0 docs/datasheet/cpu_dual_core.adoc
+40 −54 docs/datasheet/soc.adoc
+3 −3 docs/datasheet/soc_dcache.adoc
+3 −3 docs/datasheet/soc_icache.adoc
+2 −2 docs/datasheet/soc_xbus.adoc
+9 −8 docs/datasheet/software.adoc
+5 −0 docs/datasheet/software_bootloader.adoc
+14 −4 docs/datasheet/software_rte.adoc
+ − docs/figures/bus_interface.png
+ − docs/figures/bus_interface_atomic.png
+ − docs/figures/neorv32_bus.png
+ − docs/figures/neorv32_ocd_complex.png
+ − docs/figures/neorv32_processor.png
+ − docs/figures/smp_system.png
+1 −1 docs/legal.adoc
+0 −1 docs/sources/bus_interface.json
+0 −25 docs/sources/bus_interface_atomic.json
+92 −56 rtl/core/neorv32_application_image.vhd
+219 −192 rtl/core/neorv32_bootloader_image.vhd
+121 −106 rtl/core/neorv32_bus.vhd
+7 −6 rtl/core/neorv32_cache.vhd
+18 −17 rtl/core/neorv32_cpu.vhd
+30 −25 rtl/core/neorv32_cpu_control.vhd
+33 −9 rtl/core/neorv32_cpu_lsu.vhd
+3 −2 rtl/core/neorv32_dma.vhd
+10 −6 rtl/core/neorv32_package.vhd
+113 −67 rtl/core/neorv32_top.vhd
+2 −2 rtl/system_integration/neorv32_vivado_ip.tcl
+3 −3 rtl/system_integration/neorv32_vivado_ip.vhd
+7 −4 sim/neorv32_tb.vhd
+1 −4 sw/bootloader/bootloader.c
+173 −141 sw/common/crt0.S
+0 −363 sw/example/atomic_test/main.c
+7 −7 sw/example/demo_clint/main.c
+1 −1 sw/example/demo_dual_core/Makefile
+202 −0 sw/example/demo_dual_core/main.c
+1 −0 sw/example/demo_dual_core/run_check.sh
+32 −0 sw/example/demo_dual_core/spinlock.c
+12 −0 sw/example/demo_dual_core/spinlock.h
+2 −2 sw/example/hello_cpp/main.cpp
+2 −2 sw/example/hello_world/main.c
+89 −96 sw/example/processor_check/main.c
+0 −1 sw/lib/include/neorv32.h
+6 −1 sw/lib/include/neorv32_aux.h
+3 −2 sw/lib/include/neorv32_clint.h
+0 −93 sw/lib/include/neorv32_cpu_amo.h
+1 −1 sw/lib/include/neorv32_cpu_csr.h
+5 −16 sw/lib/include/neorv32_rte.h
+418 −1 sw/lib/source/neorv32_aux.c
+30 −19 sw/lib/source/neorv32_clint.c
+0 −338 sw/lib/source/neorv32_cpu_amo.c
+121 −446 sw/lib/source/neorv32_rte.c
+9 −5 sw/openocd/openocd_neorv32.cfg
+67 −0 sw/openocd/openocd_neorv32.dual_core.cfg
+9 −0 sw/svd/neorv32.svd
4 changes: 2 additions & 2 deletions src/neorv32_verilog_wrapper.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 --
-- Copyright (c) NEORV32 contributors. --
-- Copyright (c) 2020 - 2024 Stephan Nolting. All rights reserved. --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved. --
-- Licensed under the BSD-3-Clause license, see LICENSE for details. --
-- SPDX-License-Identifier: BSD-3-Clause --
-- ================================================================================ --
Expand Down Expand Up @@ -44,7 +44,7 @@ begin
RISCV_ISA_C => true, -- implement compressed extension
RISCV_ISA_M => true, -- implement mul/div extension
RISCV_ISA_U => true, -- implement user mode extension
RISCV_ISA_Zalrsc => true, -- implement atomic reservation-set extension
RISCV_ISA_Zaamo => true, -- implement atomic memory operations extension
RISCV_ISA_Zba => true, -- implement shifted-add bit-manipulation extension
RISCV_ISA_Zbb => true, -- implement basic bit-manipulation extension
RISCV_ISA_Zbkb => true, -- implement bit-manipulation instructions for cryptography
Expand Down