Merge pull request #199 from stnolting/dependabot/submodules/neorv32-…

…06f3177 [Dependabot]: Bump neorv32 from `f9a2801` to `06f3177`
stnolting · Nov 3, 2024 · 3873ab6 · 3873ab6
2 parents 372b2f3 + 5ad4108
commit 3873ab6
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/neorv32 b/neorv32
diff --git a/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd b/osflow/devices/ice40/neorv32_imem.ice40up_spram.vhd
@@ -22,8 +22,8 @@ use iCE40.components.all;
 
 entity neorv32_imem is
   generic (
-    IMEM_SIZE    : natural; -- processor-internal instruction memory size in bytes, has to be a power of 2
-    IMEM_AS_IROM : boolean  -- implement IMEM as pre-initialized read-only memory?
+    IMEM_SIZE : natural; -- processor-internal instruction memory size in bytes, has to be a power of 2
+    IMEM_INIT : boolean  -- implement IMEM as pre-initialized read-only memory?
   );
   port (
     clk_i     : in  std_ulogic; -- global clock line
@@ -66,7 +66,7 @@ begin
   -- Sanity Checks --------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
   assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note;
-  assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure;
+  assert not (IMEM_INIT = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure;
   assert not (IMEM_SIZE /= 64*1024) report "NEORV32 PROCESSOR CONFIG NOTE: IMEM SPRAM has a fixed physical size of 64kB." severity note;
+27 −61		.github/workflows/Processor.yml
+3 −1		CHANGELOG.md
+3 −1		README.md
+1 −1		docs/datasheet/cpu_csr.adoc
+4 −4		docs/datasheet/overview.adoc
+44 −47		docs/datasheet/rationale.adoc
+62 −39		docs/datasheet/soc.adoc
+11 −15		docs/datasheet/soc_bootrom.adoc
+1 −1		docs/datasheet/soc_dmem.adoc
+20 −19		docs/datasheet/soc_imem.adoc
+33 −32		docs/datasheet/soc_sysinfo.adoc
+3 −3		docs/datasheet/software.adoc
+1 −1		docs/datasheet/software_bootloader.adoc
+ −		docs/figures/neorv32_boot_configurations.png
+8 −1		docs/userguide/packaging_vivado.adoc
+17 −96		docs/userguide/simulating_the_processor.adoc
+11 −6		rtl/core/neorv32_application_image.vhd
+14 −9		rtl/core/neorv32_bootloader_image.vhd
+1 −1		rtl/core/neorv32_bus.vhd
+1 −1		rtl/core/neorv32_cpu_control.vhd
+19 −19		rtl/core/neorv32_dmem.vhd
+31 −33		rtl/core/neorv32_imem.vhd
+6 −40		rtl/core/neorv32_package.vhd
+5 −2		rtl/core/neorv32_sysinfo.vhd
+46 −18		rtl/core/neorv32_top.vhd
+1 −1		rtl/core/neorv32_xbus.vhd
+0 −2		rtl/file_list_cpu.f
+2 −2		rtl/file_list_soc.f
+4 −3		rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd
+4 −3		rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd
+4 −3		rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd
+56 −29		rtl/system_integration/neorv32_vivado_ip.tcl
+26 −19		rtl/system_integration/neorv32_vivado_ip.vhd
+1 −1		rtl/system_integration/xbus2ahblite_bridge.vhd
+3 −2		rtl/test_setups/neorv32_test_setup_approm.vhd
+3 −2		rtl/test_setups/neorv32_test_setup_bootloader.vhd
+3 −2		rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd
+0 −24		sim/README.md
+2 −2		sim/ghdl.run.sh
+3 −3		sim/ghdl.setup.sh
+12 −0		sim/ghdl.sh
+216 −226		sim/neorv32_tb.vhd
+0 −56		sim/run.py
+0 −10		sim/simple/ghdl.sh
+0 −605		sim/simple/neorv32_tb.simple.vhd
+0 −77		sim/simple/uart_rx.simple.vhd
+11 −53		sim/uart_rx.vhd
+0 −60		sim/uart_rx_pkg.vhd
+3 −1		sw/bootloader/makefile
+15 −7		sw/common/common.mk
+1 −1		sw/example/hello_world/makefile
+1 −1		sw/example/processor_check/makefile
+45 −52		sw/image_gen/image_gen.c
+5 −2		sw/lib/include/neorv32_sysinfo.h
+16 −12		sw/lib/source/neorv32_rte.c
+2 −2		sw/lib/source/neorv32_uart.c
+5 −4		sw/svd/neorv32.svd